Replaced some verilog with IPs

block ram/rom verilog files were replaced with block memory generator IPs 100MHz clocking hdl replaced with clock wizard IP
Digilent · Jun 5, 2017 · 3b8651d · 3b8651d
1 parent e4393ec
commit 3b8651d
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Showing 12 changed files with 1,374 additions and 1,168 deletions.
diff --git a/src/hdl/OLEDCtrl.v b/src/hdl/OLEDCtrl.v
@@ -73,7 +73,7 @@ localparam ActiveToggleDispWait = 8'h26;
 localparam ActiveWrite          = 8'h27;
 localparam ActiveWriteTran      = 8'h28;
 localparam ActiveWriteWait      = 8'h29;
-//Bringdown STATES
+//BRINGDOWN STATES
 localparam BringdownDispOff     = 8'h30;
 localparam BringdownVbatOff     = 8'h31;
 localparam BringdownDelay       = 8'h32;
@@ -167,40 +167,28 @@ assign pbuf_write_en = (state == ActiveWrite) ? 1'b1 : 1'b0;
 assign pbuf_write_addr = temp_write_base_addr + write_byte_count;
 
 //read only memory for character bitmaps
-block_rom #(
-    .DATA_WIDTH (8),
-    .ADDR_WIDTH (10),
-    .FILENAME   ("charLib.dat")
-) CHAR_LIB_COMP (
-    .clk        (clk),
-    .addr       (char_lib_addr),
-    .dout       (pbuf_write_data)
+charLib CHAR_LIB (
+    .clka(clk),
+    .addra(char_lib_addr),
+    .douta(pbuf_write_data)
 );
 
 //pixel buffer
-block_ram #(
-    .DATA_WIDTH     (8),
-    .ADDR_WIDTH     (9),
-    .INIT_FROM_FILE ("false"),
-    .INIT_FILENAME  ()
-) BYTE_BUFFER (
-    .clk            (clk),
-    .write_en       (pbuf_write_en),
-    .write_addr     (pbuf_write_addr),
-    .write_data     (pbuf_write_data),
-    .read_addr      (pbuf_read_addr),
-    .read_data      (pbuf_read_data)
+pixel_buffer PIXEL_BUFFER (
+    .clka  (clk),
+    .wea   (pbuf_write_en),
+    .addra (pbuf_write_addr),
+    .dina  (pbuf_write_data),
+    .clkb  (clk),
+    .addrb (pbuf_read_addr),
+    .doutb (pbuf_read_data)
 );
 
 //initialization sequence op code look up
-block_rom #(
-    .DATA_WIDTH(16),
-    .ADDR_WIDTH(4),
-    .FILENAME("init_sequence.dat")
-) init_sequence (
-    .clk(clk),
-    .addr(startup_count),
-    .dout(init_operation)
+init_sequence_rom INIT_SEQ (
+    .clka(clk),
+    .addra(startup_count),
+    .douta(init_operation)
 );
 
 //handshake flags, ready means associated start will be accepted

diff --git a/src/hdl/block_ram.v b/src/hdl/block_ram.v
diff --git a/src/hdl/block_rom.v b/src/hdl/block_rom.v
diff --git a/src/hdl/top.v b/src/hdl/top.v
@@ -47,29 +47,28 @@ module top(
     localparam str1=" I am the OLED  ", str1len=16;
     localparam str2=" Display Demo   ", str2len=16;
     localparam str3=" for Digilent's ", str3len=16;
-    localparam str4=" Genesys2       ", str4len=16;
+    localparam str4=" Genesys 2      ", str4len=16;
 
-	wire clk200M;
-	reg clk=0;
+    localparam AUTO_START = 1; // determines whether the OLED will be automatically initialized when the board is programmed
+
+	wire clk;
 
     //state machine registers.
-    reg [2:0] state = Idle;
+    reg [2:0] state = (AUTO_START == 1) ? Init : Idle;
     reg [5:0] count = 0;//loop index variable
     reg       once = 0;//bool to see if we have set up local pixel memory in this session
 
     //oled control signals
     //command start signals, assert high to start command
     reg        update_start = 0;        //update oled display over spi
-    reg        disp_on_start = 0;       //turn the oled display on
+    reg        disp_on_start = AUTO_START;       //turn the oled display on
     reg        disp_off_start = 0;      //turn the oled display off
     reg        toggle_disp_start = 0;   //turns on every pixel on the oled, or returns the display to before each pixel was turned on
     reg        write_start = 0;         //writes a character bitmap into local memory
-
     //data signals for oled controls
     reg        update_clear = 0;        //when asserted high, an update command clears the display, instead of filling from memory
     reg  [8:0] write_base_addr = 0;     //location to write character to, two most significant bits are row position, 0 is topmost. bottom seven bits are X position, addressed by pixel x position.
     reg  [7:0] write_ascii_data = 0;    //ascii value of character to write to memory
-
     //active high command ready signals, appropriate start commands are ignored when these are not asserted high
     wire       disp_on_ready;
     wire       disp_off_ready;
@@ -84,19 +83,14 @@ module top(
     wire       dBtnD;   // Bottom DPad Button tied to update with clear
 
 	//create a 100MHz clock signal from 200MHz differential input.
-	IBUFGDS #(
-		.DIFF_TERM    ("FALSE"),
-		.IBUF_LOW_PWR ("TRUE"),
-		.IOSTANDARD   ("LVDS")
-	) get_clk (
-		.O  (clk200M),
-		.I  (clk_p),
-		.IB (clk_n)
-	);
-	always@(posedge clk200M) clk <= ~clk;
+	clk_wiz_0 getCLK (
+        .clk_in1_n (clk_n),
+        .clk_in1_p (clk_p),
+        .clk_out1  (clk)
+    );
 
 	//instantiate OLED controller
-    OLEDCtrl uut (
+    OLEDCtrl m_OLEDCtrl (
         .clk                (clk),              
         .write_start        (write_start),      
         .write_ascii_data   (write_ascii_data), 
@@ -162,7 +156,7 @@ module top(
         .B(rst)
     );
 
-    assign led = update_ready;//display whether btnU, BtnD controls are available.
+    assign led = update_ready;//display whether btnU, BtnD controls are available..
     assign init_done = disp_off_ready | toggle_disp_ready | write_ready | update_ready;//parse ready signals for clarity
     assign init_ready = disp_on_ready;
     always@(posedge clk)
@@ -186,7 +180,6 @@ module top(
                 end else if (once == 0 && write_ready) begin
                     write_start <= 1'b1;
                     write_base_addr <= 'b0;
-//                    write_ascii_data <= 8'd65;
                     state <= WriteWait;
                 end else if (once == 1 && dBtnU == 1) begin
                     update_start <= 1'b1;