ASM_Tests: Test F2I conversion overflow behaviour

FEX-Emu · Dec 30, 2024 · a21789d · a21789d
1 parent efd6e95
commit a21789d
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Showing 9 changed files with 97 additions and 19 deletions.
diff --git a/unittests/ASM/OpSize/66_2D.asm b/unittests/ASM/OpSize/66_2D.asm
@@ -2,7 +2,9 @@
 {
   "RegData": {
     "MM0":  "0x0000000200000001",
-    "MM1":  "0xFFFFFFFEFFFFFFFF"
+    "MM1":  "0xFFFFFFFEFFFFFFFF",
+    "MM2":  "0x8000000080000000",
+    "MM3":  "0x8000000080000000"
   }
 }
 %endif
@@ -29,12 +31,24 @@ mov [rdx + 8 * 4], rax
 mov rax, 0x5152535455565758
 mov [rdx + 8 * 5], rax
 
+mov rax, 0x7ff0000000000000
+mov [rdx + 8 * 6], rax
+mov rax, 0xfff0000000000000
+mov [rdx + 8 * 7], rax
+
+mov rax, 0x7ff8000000000000
+mov [rdx + 8 * 8], rax
+mov rax, 0x7fefffffffffffff
+mov [rdx + 8 * 9], rax
+
 movq mm0, [rdx + 8 * 4]
 movq mm1, [rdx + 8 * 4]
 
 movapd xmm2, [rdx + 8 * 0]
 
 cvtpd2pi mm0, xmm2
 cvtpd2pi mm1, [rdx + 8 * 2]
+cvtpd2pi mm2, [rdx + 8 * 6]
+cvtpd2pi mm3, [rdx + 8 * 8]
 
 hlt
diff --git a/unittests/ASM/OpSize/66_5A.asm b/unittests/ASM/OpSize/66_5A.asm
@@ -2,7 +2,9 @@
 {
   "RegData": {
     "XMM0": ["0x404000003F800000", "0x0"],
-    "XMM1": ["0x3FF0000000000000", "0x4008000000000000"]
+    "XMM1": ["0x3FF0000000000000", "0x4008000000000000"],
+    "XMM2": ["0xff8000007f800000", "0x0000000000000000"],
+    "XMM3": ["0x7f8000007fc00000", "0x0000000000000000"]
   }
 }
 %endif
@@ -19,9 +21,22 @@ mov [rdx + 8 * 2], rax
 mov rax, 0xFFFFFFFFFFFFFFFF
 mov [rdx + 8 * 3], rax
 
+mov rax, 0x7ff0000000000000
+mov [rdx + 8 * 4], rax
+mov rax, 0xfff0000000000000
+mov [rdx + 8 * 5], rax
+mov rax, 0x7ff8000000000000
+mov [rdx + 8 * 6], rax
+mov rax, 0x7fefffffffffffff
+mov [rdx + 8 * 7], rax
+
 movapd xmm0, [rdx + 8 * 2]
 movapd xmm1, [rdx]
+movapd xmm2, [rdx + 8 * 4]
+movapd xmm3, [rdx + 8 * 6]
 
 cvtpd2ps xmm0, xmm1
+cvtpd2ps xmm2, xmm2
+cvtpd2ps xmm3, xmm3
 
 hlt
diff --git a/unittests/ASM/OpSize/66_5B.asm b/unittests/ASM/OpSize/66_5B.asm
@@ -2,7 +2,8 @@
 {
   "RegData": {
     "XMM0":  ["0x0000000100000001", "0x0000000200000002"],
-    "XMM1":  ["0x0000000400000004", "0x0000000800000008"]
+    "XMM1":  ["0x0000000400000004", "0x0000000800000008"],
+    "XMM2":  ["0x8000000000000000", "0x8000000080000000"]
   }
 }
 %endif
@@ -24,6 +25,11 @@ mov [rdx + 8 * 4], rax
 mov rax, 0x5152535455565758
 mov [rdx + 8 * 5], rax
 
+mov rax, 0x7fc000007f800000
+mov [rdx + 8 * 6], rax
+mov rax, 0xff800000ff7fffee
+mov [rdx + 8 * 7], rax
+
 ; Set up MXCSR to truncate
 mov eax, 0x7F80
 mov [rdx + 8 * 6], eax
@@ -36,5 +42,6 @@ movapd xmm2, [rdx + 8 * 0]
 
 cvtps2dq xmm0, xmm2
 cvtps2dq xmm1, [rdx + 8 * 2]
+cvtps2dq xmm2, [rdx + 8 * 6]
 
 hlt
diff --git a/unittests/ASM/REPNE/F2_2D.asm b/unittests/ASM/REPNE/F2_2D.asm
@@ -4,7 +4,11 @@
     "RAX": "0x1",
     "RBX": "0x2",
     "RCX": "0x3",
-    "RDX": "0x4"
+    "RDX": "0x4",
+    "R9": "0x8000000000000000",
+    "R10": "0x8000000000000000",
+    "R11": "0x8000000000000000",
+    "R12": "0x8000000000000000"
   }
 }
 %endif
@@ -31,13 +35,27 @@ mov [rdx + 8 * 6], rax
 mov rax, 0x5152535455565758
 mov [rdx + 8 * 7], rax
 
+mov rax, 0x7ff0000000000000
+mov [rdx + 8 * 8], rax
+mov rax, 0xfff0000000000000
+mov [rdx + 8 * 9], rax
+mov rax, 0x7ff8000000000000
+mov [rdx + 8 * 10], rax
+mov rax, 0x7fefffffffffffff
+mov [rdx + 8 * 11], rax
+
+
 movapd xmm0, [rdx + 8 * 0]
 movapd xmm1, [rdx + 8 * 2]
 
 cvtsd2si eax, xmm0
 cvtsd2si rbx, xmm1
 
 cvtsd2si ecx, [rdx + 8 * 4]
+cvtsd2si r9, [rdx + 8 * 8]
+cvtsd2si r10, [rdx + 8 * 9]
+cvtsd2si r11, [rdx + 8 * 10]
+cvtsd2si r12, [rdx + 8 * 11]
 cvtsd2si rdx, [rdx + 8 * 6]
 
 hlt
diff --git a/unittests/ASM/REPNE/F2_E6.asm b/unittests/ASM/REPNE/F2_E6.asm
@@ -2,7 +2,9 @@
 {
   "RegData": {
     "XMM0":  ["0x0000000200000001", "0x0"],
-    "XMM1":  ["0xFFFFFFFEFFFFFFFF", "0x0"]
+    "XMM1":  ["0xFFFFFFFEFFFFFFFF", "0x0"],
+    "XMM2":  ["0x8000000080000000", "0x0"],
+    "XMM3":  ["0x8000000080000000", "0x0"]
   }
 }
 %endif
@@ -24,12 +26,24 @@ mov [rdx + 8 * 4], rax
 mov rax, 0x5152535455565758
 mov [rdx + 8 * 5], rax
 
+mov rax, 0x7ff0000000000000
+mov [rdx + 8 * 6], rax
+mov rax, 0xfff0000000000000
+mov [rdx + 8 * 7], rax
+ 
+mov rax, 0x7ff8000000000000
+mov [rdx + 8 * 8], rax
+mov rax, 0x7fefffffffffffff
+mov [rdx + 8 * 9], rax
+
 movapd xmm0, [rdx + 8 * 4]
 movapd xmm1, [rdx + 8 * 4]
 
 movapd xmm2, [rdx + 8 * 0]
 
 cvtpd2dq xmm0, xmm2
 cvtpd2dq xmm1, [rdx + 8 * 2]
+cvtpd2dq xmm2, [rdx + 8 * 6]
+cvtpd2dq xmm3, [rdx + 8 * 8]
 
 hlt
diff --git a/unittests/ASM/VEX/vcvtpd2dq_inexact.asm b/unittests/ASM/VEX/vcvtpd2dq_inexact.asm
@@ -5,7 +5,8 @@
     "XMM0":  ["0x0000000200000001", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
     "XMM1":  ["0xFFFFFFFEFFFFFFFF", "0x0000000000000000", "0x0000000000000000", "0x0000000000000000"],
     "XMM3":  ["0x0000000200000001", "0x0000000200000001", "0x0000000000000000", "0x0000000000000000"],
-    "XMM4":  ["0xFFFFFFFEFFFFFFFF", "0xFFFFFFFEFFFFFFFF", "0x0000000000000000", "0x0000000000000000"]
+    "XMM4":  ["0xFFFFFFFEFFFFFFFF", "0xFFFFFFFEFFFFFFFF", "0x0000000000000000", "0x0000000000000000"],
+    "XMM5":  ["0x8000000080000000", "0x8000000080000000", "0x0000000000000000", "0x0000000000000000"]
   }
 }
 %endif
@@ -22,6 +23,8 @@ vcvtpd2dq xmm1, oword [rdx + 32 * 1]
 vcvtpd2dq xmm3, ymm2
 vcvtpd2dq xmm4, yword [rdx + 32 * 1]
 
+vcvtpd2dq xmm5, yword [rdx + 32 * 3]
+
 hlt
 
 align 32
@@ -40,3 +43,8 @@ dq 0x4142434445464748
 dq 0x5152535455565758
 dq 0x4142434445464748
 dq 0x5152535455565758
+
+dq 0x7ff0000000000000
+dq 0xfff0000000000000
+dq 0x7ff8000000000000
+dq 0x7fefffffffffffff
diff --git a/unittests/ASM/VEX/vcvtpd2ps.asm b/unittests/ASM/VEX/vcvtpd2ps.asm
@@ -11,7 +11,8 @@
     "XMM10": ["0x4214ADB642B062C4", "0x41245B0E42461AA5", "0x0000000000000000", "0x0000000000000000"],
     "XMM11": ["0x41A1B712429B697F", "0x42252CF2411CE3BD", "0x0000000000000000", "0x0000000000000000"],
     "XMM12": ["0x42662BE34176837B", "0x425E2C0D4119C75A", "0x0000000000000000", "0x0000000000000000"],
-    "XMM13": ["0x409C30014253A13B", "0x4041495242910EC1", "0x0000000000000000", "0x0000000000000000"]
+    "XMM13": ["0x409C30014253A13B", "0x4041495242910EC1", "0x0000000000000000", "0x0000000000000000"],
+    "XMM14": ["0xff8000007f800000", "0x7f8000007fc00000", "0x0000000000000000", "0x0000000000000000"]
   }
 }
 %endif
@@ -29,6 +30,7 @@ vcvtpd2ps xmm10, yword [rdx + 32 * 10]
 vcvtpd2ps xmm11, yword [rdx + 32 * 11]
 vcvtpd2ps xmm12, yword [rdx + 32 * 12]
 vcvtpd2ps xmm13, yword [rdx + 32 * 13]
+vcvtpd2ps xmm14, yword [rdx + 32 * 14]
 
 hlt
 
@@ -75,3 +77,6 @@ dq 9.61117, 55.54302
 
 dq 52.90745, 4.88086
 dq 72.52882, 3.0201
+
+dq 0x7ff0000000000000, 0xfff0000000000000
+dq 0x7ff8000000000000, 0x7fefffffffffffff
diff --git a/unittests/ASM/VEX/vcvtps2dq_inexact.asm b/unittests/ASM/VEX/vcvtps2dq_inexact.asm
@@ -5,7 +5,8 @@
     "XMM0":  ["0x0000000100000001", "0x0000000200000002", "0x0000000000000000", "0x0000000000000000"],
     "XMM1":  ["0x0000000400000004", "0x0000000800000008", "0x0000000000000000", "0x0000000000000000"],
     "XMM3":  ["0x0000000100000001", "0x0000000200000002", "0x0000000100000001", "0x0000000200000002"],
-    "XMM4":  ["0x0000000400000004", "0x0000000800000008", "0x0000000400000004", "0x0000000800000008"]
+    "XMM4":  ["0x0000000400000004", "0x0000000800000008", "0x0000000400000004", "0x0000000800000008"],
+    "XMM5":  ["0x8000000080000000", "0x8000000080000000", "0x8000000080000000", "0x0000000000000000"]
   }
 }
 %endif
@@ -24,6 +25,7 @@ vcvtps2dq xmm1, [rdx + 32 * 1]
 
 vcvtps2dq ymm3, ymm2
 vcvtps2dq ymm4, [rdx + 32 * 1]
+vcvtps2dq ymm5, [rdx + 32 * 3]
 
 hlt
 
@@ -44,5 +46,10 @@ dq 0x5152535455565758
 dq 0x4142434445464748
 dq 0x5152535455565758
 
+dq 0x7fc000007f800000
+dq 0xff800000ff7fffee
+dq 0x7bc097cefbc097ce
+dq 0x0000000080000000
+
 .mxcsr:
-dq 0x0000000000007F80
+dq 0x0000000000007F80
diff --git a/unittests/gcc-target-tests-64/Known_Failures b/unittests/gcc-target-tests-64/Known_Failures
@@ -12,13 +12,3 @@ asm-5.c.gcc-target-test-64
 # Which turns the value in to 0xfffff2f5
 # This causes its comparison to fail
 sse2-mmx-pextrw.c.gcc-target-test-64
-
-# These tests fail because of things unrelated to the sse4.1 instructions
-sse4_1-ceil-sfix-vec.c.gcc-target-test-64
-sse4_1-ceilf-sfix-vec.c.gcc-target-test-64
-sse4_1-floor-sfix-vec.c.gcc-target-test-64
-sse4_1-floorf-sfix-vec.c.gcc-target-test-64
-sse4_1-rint-sfix-vec.c.gcc-target-test-64
-sse4_1-rintf-sfix-vec.c.gcc-target-test-64
-sse4_1-round-sfix-vec.c.gcc-target-test-64
-sse4_1-roundf-sfix-vec.c.gcc-target-test-64