Adding all files

ClockDivider.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:26:19 04/17/2016 
+// Design Name: 
+// Module Name:    ClockDivider 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+// Adjustable clock divider - outouts a pulse signal at specified period by using the hardware clock signal with a counter
+// that is divided into a half with 0 output and a half with 1 output
+module ClockDivider(
+input in_clk,
+input[26:0] clk_period,
+output reg out_clk
+    );
+	reg[26:0] count;
+
+	always @ (posedge in_clk) begin
+		if (count == clk_period - 1'b1)
+			count <= 0;
+		else
+			count <= count + 1'b1;
+		if (count >= (clk_period - 1'b1)/2)
+			out_clk <= 1;
+		else
+			out_clk <= 0;
+
+	end
+
+endmodule

Counter.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:55:16 04/13/2016 
+// Design Name: 
+// Module Name:    Counter 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Counter(count_out, count_in, count_up, max_count);
+
+// This module counts up or down by 1 depending on the state of the input count_dir
+// Count speed is handled outside of this module, since all it does it determine how
+// frequently this module is used
+
+	input[11:0] count_in;
+	input[11:0] max_count;
+
+	//0 will count down, 1 will count up
+	input count_up;
+
+	output reg[11:0] count_out;
+
+	always @ (*)
+	begin
+	if (count_in == max_count && count_up == 1'b1)
+			assign count_out = 6'b000000;
+	else
+		assign count_out = count_in + count_up + count_up - 1'b1;
+	end
+
+endmodule

Debounce.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    03:04:36 04/15/2016 
+// Design Name: 
+// Module Name:    Debounce 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Debounce(
+    input clk,
+    input PB,  // "PB" is the glitchy, asynchronous to clk, active high push-button signal
+
+    // from which we make an output synchronous to the clock
+    output PB_down  // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
+);
+
+reg PB_state;
+// First use two flip-flops to synchronize the PB signal the "clk" clock domain
+reg PB_sync_0;  always @(posedge clk) PB_sync_0 <= PB;  
+reg PB_sync_1;  always @(posedge clk) PB_sync_1 <= PB_sync_0;
+
+// Next declare a 16-bits counter
+reg [17:0] PB_cnt;
+
+// When the push-button is pushed or released, we increment the counter
+// The counter has to be maxed out before we decide that the push-button state has changed
+
+wire PB_idle = (PB_state==PB_sync_1);
+wire PB_cnt_max = &PB_cnt;	// true when all bits of PB_cnt are 1's
+
+always @(posedge clk)
+if(PB_idle)
+    PB_cnt <= 0;  // nothing's going on
+else
+begin
+    PB_cnt <= PB_cnt + 18'd1;  // something's going on, increment the counter
+    if(PB_cnt_max) PB_state <= ~PB_state;  // if the counter is maxed out, PB changed!
+end
+
+assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
+endmodule

KitchenTimer.bld

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+Release 14.2 ngdbuild P.28xd (nt64)
+Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
+
+Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
+-intstyle ise -dd _ngo -nt timestamp -uc KitchenTimer.ucf -p xc6slx16-csg324-3
+KitchenTimer.ngc KitchenTimer.ngd
+
+Reading NGO file "X:/My Documents/EC311/Labs/ProjectFinal/KitchenTimer.ngc" ...
+Gathering constraint information from source properties...
+Done.
+
+Annotating constraints to design from ucf file "KitchenTimer.ucf" ...
+Resolving constraint associations...
+Checking Constraint Associations...
+Done...
+
+Checking expanded design ...
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+  Number of errors:     0
+  Number of warnings:   0
+
+Total memory usage is 159352 kilobytes
+
+Writing NGD file "KitchenTimer.ngd" ...
+Total REAL time to NGDBUILD completion:  3 sec
+Total CPU time to NGDBUILD completion:   2 sec
+
+Writing NGDBUILD log file "KitchenTimer.bld"...