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Kogepan229 committed Dec 19, 2024
2 parents c0d6a80 + e149e43 commit 2ee7952
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Showing 8 changed files with 188 additions and 318 deletions.
159 changes: 3 additions & 156 deletions Cargo.lock

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1 change: 0 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,6 @@ edition = "2021"

[dependencies]
spin_sleep = "1.3.0"
tokio = { version = "1.42", features = ["full"] }
nom = "7.1.3"
anyhow = { version = "1.0", features = ["backtrace"] }
clap = { version = "4.5", features = ["derive"] }
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11 changes: 6 additions & 5 deletions src/bus.rs
Original file line number Diff line number Diff line change
@@ -1,10 +1,9 @@
use std::{cell::RefCell, rc::Weak};
use std::{cell::RefCell, rc::Weak, sync::mpsc::Sender};

use crate::{
memory::{create_memory, Memory, MEMORY_END_ADDR, MEMORY_START_ADDR},
modules::ModuleManager,
registers::DRCRA,
socket::send_addr_value_u8,
registers::DRCRA, // socket::send_addr_value_u8,
};
use anyhow::{bail, Result};

Expand Down Expand Up @@ -59,6 +58,7 @@ pub const IO_REGISTERS2_EMC1_SIZE: usize = (IO_REGISTERS2_EMC1_END_ADDR - IO_REG

#[derive(Clone)]
pub struct Bus {
pub message_tx: Option<Sender<String>>,
pub module_manager: Weak<RefCell<ModuleManager>>,
pub memory: Memory,
pub exception_handling_vector: Box<[u8]>,
Expand All @@ -70,6 +70,7 @@ pub struct Bus {
impl Bus {
pub fn new(module_manager: Weak<RefCell<ModuleManager>>) -> Self {
Bus {
message_tx: None,
module_manager,
memory: create_memory(),
exception_handling_vector: vec![0; VENCTOR_SIZE].into_boxed_slice(),
Expand All @@ -87,7 +88,7 @@ impl Bus {
if addr >= 0xfee000 && addr <= 0xfee00a {
let previous = self.read(addr)?;
if value != previous {
send_addr_value_u8(addr, value);
self.send_addr_value_u8(addr, value)?;
}
}
(*self.module_manager.upgrade().unwrap()).borrow_mut().write_registers(addr, value);
Expand All @@ -100,7 +101,7 @@ impl Bus {
if addr >= 0xffffd0 && addr <= 0xffffda {
let previous = self.read(addr)?;
if value != previous {
send_addr_value_u8(addr, value);
self.send_addr_value_u8(addr, value)?;
}
}
(*self.module_manager.upgrade().unwrap()).borrow_mut().write_registers(addr, value);
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