AND

Kogepan229 · Dec 22, 2023 · a3e8a3e · a3e8a3e
1 parent 9ab6c24
commit a3e8a3e
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Showing 2 changed files with 26 additions and 23 deletions.
diff --git a/src/cpu.rs b/src/cpu.rs
@@ -195,7 +195,7 @@ impl Cpu {
                     match (opcode2 >> 8) as u8 {
                         0x64 => return self.or_l_rn(opcode, opcode2),
                         0x65 => return self.xor_l_rn(opcode, opcode2),
-                        0x66 => return self.and_l_rn(opcode, opcode2),
+                        0x66 => return self.and_l_rn(opcode, opcode2).await,
                         _ => unimpl!(opcode, self.pc),
                     }
                 }
@@ -430,9 +430,9 @@ impl Cpu {
             0x15 => return self.xor_b_rn(opcode),
             0x65 => return self.xor_w_rn(opcode),
 
-            0xe0..=0xef => return self.and_b_imm(opcode),
-            0x16 => return self.and_b_rn(opcode),
-            0x66 => return self.and_w_rn(opcode),
+            0xe0..=0xef => return self.and_b_imm(opcode).await,
+            0x16 => return self.and_b_rn(opcode).await,
+            0x66 => return self.and_w_rn(opcode).await,
 
             0x90..=0x9f => return self.addx_imm(opcode).await,
             0x0e => return self.addx_rn(opcode).await,

diff --git a/src/cpu/instruction/and.rs b/src/cpu/instruction/and.rs
@@ -1,8 +1,8 @@
-use crate::cpu::{Cpu, CCR};
+use crate::cpu::{Cpu, StateType, CCR};
 use anyhow::{Context as _, Result};
 
 impl Cpu {
-    pub(in super::super) fn and_b_imm(&mut self, opcode: u16) -> Result<usize> {
+    pub(in super::super) async fn and_b_imm(&mut self, opcode: u16) -> Result<u8> {
         let register = Cpu::get_nibble_opcode(opcode, 2)?;
         let result = self.read_rn_b(register)? & opcode as u8;
         self.write_rn_b(register, result)?;
@@ -17,10 +17,10 @@ impl Cpu {
             self.write_ccr(CCR::Z, 0);
         }
         self.write_ccr(CCR::V, 0);
-        Ok(2)
+        Ok(self.calc_state(StateType::I, 1).await?)
     }
 
-    pub(in super::super) fn and_b_rn(&mut self, opcode: u16) -> Result<usize> {
+    pub(in super::super) async fn and_b_rn(&mut self, opcode: u16) -> Result<u8> {
         let register_src = Cpu::get_nibble_opcode(opcode, 3)?;
         let register_dest = Cpu::get_nibble_opcode(opcode, 4)?;
         let result = self.read_rn_b(register_src)? & self.read_rn_b(register_dest)?;
@@ -36,13 +36,13 @@ impl Cpu {
             self.write_ccr(CCR::Z, 0);
         }
         self.write_ccr(CCR::V, 0);
-        Ok(2)
+        Ok(self.calc_state(StateType::I, 1).await?)
     }
 
-    pub(in super::super) async fn and_w_imm(&mut self, opcode: u16) -> Result<usize> {
+    pub(in super::super) async fn and_w_imm(&mut self, opcode: u16) -> Result<u8> {
         let opcode2 = self.fetch().await;
 
-        let mut f = || -> Result<usize> {
+        let mut f = || -> Result<()> {
             let register = Cpu::get_nibble_opcode(opcode, 4)?;
             let result = self.read_rn_w(register)? & opcode2;
             self.write_rn_w(register, result)?;
@@ -57,12 +57,13 @@ impl Cpu {
                 self.write_ccr(CCR::Z, 0);
             }
             self.write_ccr(CCR::V, 0);
-            return Ok(4);
+            return Ok(());
         };
-        f().with_context(|| format!("opcode2(imm) [{:x}]", opcode2))
+        f().with_context(|| format!("opcode2(imm) [{:x}]", opcode2));
+        Ok(self.calc_state(StateType::I, 2).await?)
     }
 
-    pub(in super::super) fn and_w_rn(&mut self, opcode: u16) -> Result<usize> {
+    pub(in super::super) async fn and_w_rn(&mut self, opcode: u16) -> Result<u8> {
         let register_src = Cpu::get_nibble_opcode(opcode, 3)?;
         let register_dest = Cpu::get_nibble_opcode(opcode, 4)?;
         let result = self.read_rn_w(register_src)? & self.read_rn_w(register_dest)?;
@@ -78,13 +79,13 @@ impl Cpu {
             self.write_ccr(CCR::Z, 0);
         }
         self.write_ccr(CCR::V, 0);
-        Ok(2)
+        Ok(self.calc_state(StateType::I, 1).await?)
     }
 
-    pub(in super::super) async fn and_l_imm(&mut self, opcode: u16) -> Result<usize> {
+    pub(in super::super) async fn and_l_imm(&mut self, opcode: u16) -> Result<u8> {
         let imm = ((self.fetch().await as u32) << 16) | self.fetch().await as u32;
 
-        let mut f = || -> Result<usize> {
+        let mut f = || -> Result<()> {
             let register = Cpu::get_nibble_opcode(opcode, 4)?;
             let result = self.read_rn_l(register)? & imm;
             self.write_rn_l(register, result)?;
@@ -99,13 +100,14 @@ impl Cpu {
                 self.write_ccr(CCR::Z, 0);
             }
             self.write_ccr(CCR::V, 0);
-            return Ok(6);
+            return Ok(());
         };
-        f().with_context(|| format!("imm(opcode2, 3) [{:x}]", imm))
+        f().with_context(|| format!("imm(opcode2, 3) [{:x}]", imm));
+        Ok(self.calc_state(StateType::I, 3).await?)
     }
 
-    pub(in super::super) fn and_l_rn(&mut self, _opcode: u16, opcode2: u16) -> Result<usize> {
-        let mut f = || -> Result<usize> {
+    pub(in super::super) async fn and_l_rn(&mut self, _opcode: u16, opcode2: u16) -> Result<u8> {
+        let mut f = || -> Result<()> {
             let register_src = Cpu::get_nibble_opcode(opcode2, 3)?;
             let register_dest = Cpu::get_nibble_opcode(opcode2, 4)?;
             let result = self.read_rn_l(register_src)? & self.read_rn_l(register_dest)?;
@@ -121,9 +123,10 @@ impl Cpu {
                 self.write_ccr(CCR::Z, 0);
             }
             self.write_ccr(CCR::V, 0);
-            return Ok(4);
+            return Ok(());
         };
-        f().with_context(|| format!("opcode2 [{:x}]", opcode2))
+        f().with_context(|| format!("opcode2 [{:x}]", opcode2));
+        Ok(self.calc_state(StateType::I, 2).await?)
     }
 }