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FakeCPU.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 00:15:14 December 03, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# FakeCPU_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSXFC6D6F31C6
set_global_assignment -name TOP_LEVEL_ENTITY FakeCPU
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:15:14 DECEMBER 03, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "10 ns" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH FakeCPU -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME ALU -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_vlg_tst -section_id ALU
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_NAME FakeCPU -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id FakeCPU
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME FakeCPU_vlg_tst -section_id FakeCPU
set_location_assignment PIN_AB21 -to hex5[6]
set_location_assignment PIN_AF19 -to hex5[5]
set_location_assignment PIN_AE19 -to hex5[4]
set_location_assignment PIN_AG20 -to hex5[3]
set_location_assignment PIN_AF20 -to hex5[2]
set_location_assignment PIN_AG21 -to hex5[1]
set_location_assignment PIN_AF21 -to hex5[0]
set_location_assignment PIN_AH22 -to hex4[6]
set_location_assignment PIN_AF23 -to hex4[5]
set_location_assignment PIN_AG23 -to hex4[4]
set_location_assignment PIN_AE23 -to hex4[3]
set_location_assignment PIN_AE22 -to hex4[2]
set_location_assignment PIN_AG22 -to hex4[1]
set_location_assignment PIN_AD21 -to hex4[0]
set_location_assignment PIN_W16 -to hex2[6]
set_location_assignment PIN_AF18 -to hex2[5]
set_location_assignment PIN_Y18 -to hex2[4]
set_location_assignment PIN_Y17 -to hex2[3]
set_location_assignment PIN_AA18 -to hex2[2]
set_location_assignment PIN_AB17 -to hex2[1]
set_location_assignment PIN_AA21 -to hex2[0]
set_location_assignment PIN_AD20 -to hex3[6]
set_location_assignment PIN_AA19 -to hex3[5]
set_location_assignment PIN_AC20 -to hex3[4]
set_location_assignment PIN_AA20 -to hex3[3]
set_location_assignment PIN_AD19 -to hex3[2]
set_location_assignment PIN_W19 -to hex3[1]
set_location_assignment PIN_Y19 -to hex3[0]
set_location_assignment PIN_AF14 -to clk_50
set_location_assignment PIN_AB25 -to ps2_clk
set_location_assignment PIN_AA25 -to ps2_dat
set_location_assignment PIN_AF16 -to hex1[6]
set_location_assignment PIN_V16 -to hex1[5]
set_location_assignment PIN_AE16 -to hex1[4]
set_location_assignment PIN_AD17 -to hex1[3]
set_location_assignment PIN_AE18 -to hex1[2]
set_location_assignment PIN_AE17 -to hex1[1]
set_location_assignment PIN_V17 -to hex1[0]
set_location_assignment PIN_W17 -to hex0[6]
set_location_assignment PIN_V18 -to hex0[5]
set_location_assignment PIN_AG17 -to hex0[4]
set_location_assignment PIN_AG16 -to hex0[3]
set_location_assignment PIN_AH17 -to hex0[2]
set_location_assignment PIN_AG18 -to hex0[1]
set_location_assignment PIN_AH18 -to hex0[0]
set_location_assignment PIN_AC22 -to ledr[9]
set_location_assignment PIN_AB22 -to ledr[8]
set_location_assignment PIN_AF24 -to ledr[7]
set_location_assignment PIN_AE24 -to ledr[6]
set_location_assignment PIN_AF25 -to ledr[5]
set_location_assignment PIN_AG25 -to ledr[4]
set_location_assignment PIN_AD24 -to ledr[3]
set_location_assignment PIN_AC23 -to ledr[2]
set_location_assignment PIN_AB23 -to ledr[1]
set_location_assignment PIN_AA24 -to ledr[0]
set_location_assignment PIN_AA30 -to sw[9]
set_location_assignment PIN_AC29 -to sw[8]
set_location_assignment PIN_AD30 -to sw[7]
set_location_assignment PIN_AC28 -to sw[6]
set_location_assignment PIN_V25 -to sw[5]
set_location_assignment PIN_W25 -to sw[4]
set_location_assignment PIN_AC30 -to sw[3]
set_location_assignment PIN_AB28 -to sw[2]
set_location_assignment PIN_Y27 -to sw[1]
set_location_assignment PIN_AB30 -to sw[0]
set_location_assignment PIN_AA15 -to key[3]
set_location_assignment PIN_AA14 -to key[2]
set_location_assignment PIN_AK4 -to key[1]
set_location_assignment PIN_AJ4 -to key[0]
set_location_assignment PIN_AK16 -to vga_b[7]
set_location_assignment PIN_AJ16 -to vga_b[6]
set_location_assignment PIN_AJ17 -to vga_b[5]
set_location_assignment PIN_AH19 -to vga_b[4]
set_location_assignment PIN_AJ19 -to vga_b[3]
set_location_assignment PIN_AH20 -to vga_b[2]
set_location_assignment PIN_AJ20 -to vga_b[1]
set_location_assignment PIN_AJ21 -to vga_b[0]
set_location_assignment PIN_AK22 -to vga_blank_n
set_location_assignment PIN_AK21 -to vga_clk
set_location_assignment PIN_AH23 -to vga_g[7]
set_location_assignment PIN_AK23 -to vga_g[6]
set_location_assignment PIN_AH24 -to vga_g[5]
set_location_assignment PIN_AJ24 -to vga_g[4]
set_location_assignment PIN_AK24 -to vga_g[3]
set_location_assignment PIN_AH25 -to vga_g[2]
set_location_assignment PIN_AJ25 -to vga_g[1]
set_location_assignment PIN_AK26 -to vga_g[0]
set_location_assignment PIN_AK19 -to vga_hs
set_location_assignment PIN_AJ26 -to vga_r[7]
set_location_assignment PIN_AG26 -to vga_r[6]
set_location_assignment PIN_AF26 -to vga_r[5]
set_location_assignment PIN_AH27 -to vga_r[4]
set_location_assignment PIN_AJ27 -to vga_r[3]
set_location_assignment PIN_AK27 -to vga_r[2]
set_location_assignment PIN_AK28 -to vga_r[1]
set_location_assignment PIN_AK29 -to vga_r[0]
set_location_assignment PIN_AJ22 -to vga_sync_n
set_location_assignment PIN_AK18 -to vga_vs
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/ALU.vt -section_id ALU
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/FakeCPU.vt -section_id FakeCPU
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name VERILOG_FILE GFX_Controller.v
set_global_assignment -name VERILOG_FILE clkgen.v
set_global_assignment -name VERILOG_FILE Instr_Reciver.v
set_global_assignment -name VERILOG_FILE FakeCPU.v
set_global_assignment -name VERILOG_FILE ALU.v
set_global_assignment -name VERILOG_FILE REG.v
set_global_assignment -name QIP_FILE MMemory.qip
set_global_assignment -name VERILOG_FILE Decode.v
set_global_assignment -name VERILOG_FILE PC_register.v
set_global_assignment -name VERILOG_FILE MM_Manager.v
set_global_assignment -name VERILOG_TEST_BENCH_FILE simulation/modelsim/FakeCPU.vt
set_global_assignment -name VERILOG_TEST_BENCH_FILE simulation/modelsim/ALU.vt
set_global_assignment -name VERILOG_FILE simulation/modelsim/GFXMem.v
set_global_assignment -name VERILOG_FILE PS2_Keyboard.v
set_global_assignment -name VERILOG_FILE VGA_Controller.v
set_global_assignment -name VERILOG_FILE KBD_Handler.v
set_global_assignment -name QIP_FILE SW_Rom.qip
set_global_assignment -name QIP_FILE Registers.qip
set_global_assignment -name QIP_FILE GFXMemory.qip
set_global_assignment -name QIP_FILE FontROM.qip
set_global_assignment -name SOURCE_FILE db/FakeCPU.cmp.rdb
set_global_assignment -name QIP_FILE KeyTable.qip
set_global_assignment -name QIP_FILE KeyTable_Shift.qip
set_global_assignment -name QIP_FILE LPM_DIVIDE_Unsigned.qip
set_global_assignment -name QIP_FILE LPM_MULT_Unsigned.qip
set_global_assignment -name QIP_FILE LPM_MULT_Signed.qip
set_global_assignment -name QIP_FILE LPM_DIVIDE_Signed.qip
set_global_assignment -name CDF_FILE FakeCPU.cdf
set_global_assignment -name MIF_FILE MMemory.mif
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top