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simulation/modelsim
simulation/modelsim
 
 
ALU.v
ALU.v
 
 
BMPFont.hex
BMPFont.hex
 
 
Decode.v
Decode.v
 
 
FakeCPU.cdf
FakeCPU.cdf
 
 
FakeCPU.qpf
FakeCPU.qpf
 
 
FakeCPU.qsf
FakeCPU.qsf
 
 
FakeCPU.qws
FakeCPU.qws
 
 
FakeCPU.v
FakeCPU.v
 
 
FontROM.qip
FontROM.qip
 
 
FontROM.v
FontROM.v
 
 
FontROM_bb.v
FontROM_bb.v
 
 
GFXMemory.qip
GFXMemory.qip
 
 
GFXMemory.v
GFXMemory.v
 
 
GFXMemory_bb.v
GFXMemory_bb.v
 
 
GFX_Controller.v
GFX_Controller.v
 
 
Instr_Reciver.v
Instr_Reciver.v
 
 
KBD_Handler.v
KBD_Handler.v
 
 
KeyTable.mif
KeyTable.mif
 
 
KeyTable.qip
KeyTable.qip
 
 
KeyTable.v
KeyTable.v
 
 
KeyTable_Shift.mif
KeyTable_Shift.mif
 
 
KeyTable_Shift.qip
KeyTable_Shift.qip
 
 
KeyTable_Shift.v
KeyTable_Shift.v
 
 
KeyTable_Shift_bb.v
KeyTable_Shift_bb.v
 
 
KeyTable_bb.v
KeyTable_bb.v
 
 
LICENSE
LICENSE
 
 
LPM_DIVIDE_Signed.qip
LPM_DIVIDE_Signed.qip
 
 
LPM_DIVIDE_Signed.v
LPM_DIVIDE_Signed.v
 
 
LPM_DIVIDE_Signed_bb.v
LPM_DIVIDE_Signed_bb.v
 
 
LPM_DIVIDE_Unsigned.qip
LPM_DIVIDE_Unsigned.qip
 
 
LPM_DIVIDE_Unsigned.v
LPM_DIVIDE_Unsigned.v
 
 
LPM_DIVIDE_Unsigned_bb.v
LPM_DIVIDE_Unsigned_bb.v
 
 
LPM_MULT_Signed.qip
LPM_MULT_Signed.qip
 
 
LPM_MULT_Signed.v
LPM_MULT_Signed.v
 
 
LPM_MULT_Signed_bb.v
LPM_MULT_Signed_bb.v
 
 
LPM_MULT_Unsigned.qip
LPM_MULT_Unsigned.qip
 
 
LPM_MULT_Unsigned.v
LPM_MULT_Unsigned.v
 
 
LPM_MULT_Unsigned_bb.v
LPM_MULT_Unsigned_bb.v
 
 
MM_Manager.v
MM_Manager.v
 
 
MMemory.mif
MMemory.mif
 
 
MMemory.qip
MMemory.qip
 
 
MMemory.v
MMemory.v
 
 
MMemory_bb.v
MMemory_bb.v
 
 
PC_register.v
PC_register.v
 
 
PS2_Keyboard.v
PS2_Keyboard.v
 
 
README.md
README.md
 
 
REG.v
REG.v
 
 
Registers.qip
Registers.qip
 
 
Registers.v
Registers.v
 
 
Registers_bb.v
Registers_bb.v
 
 
SW_Rom.hex
SW_Rom.hex
 
 
SW_Rom.qip
SW_Rom.qip
 
 
SW_Rom.v
SW_Rom.v
 
 
SW_Rom_bb.v
SW_Rom_bb.v
 
 
VGA_Controller.v
VGA_Controller.v
 
 
clkgen.v
clkgen.v
 
 
fib.mif
fib.mif
 
 
func_test.asm
func_test.asm
 
 
keyboard_test.asm
keyboard_test.asm
 
 

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FakeCPU

A fake cpu made by verilog

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A fake cpu made by verilog

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GPL-3.0 license
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