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A Verilog-based implementation of Depth-First Search (DFS) algorithm and RISC-V processor. The RISC-V processor is uniquely crafted in three distinct architectures, namely Single-Cycle, Multi-Cycle, and Pipeline.

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Name		Name	Last commit message	Last commit date
Latest commit History 22 Commits
CA1-Rat In Maze		CA1-Rat In Maze
CA2-RISC-V Single-Cycle		CA2-RISC-V Single-Cycle
CA3-RISC-V Multi-Cycle		CA3-RISC-V Multi-Cycle
CA4-RISC-V Pipeline		CA4-RISC-V Pipeline
LICENSE		LICENSE
README.md		README.md

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Computer-Architecture-Course-Projects-S2023

Contributors:

Mobina Mehrazar

Mohammad Nemati

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A Verilog-based implementation of Depth-First Search (DFS) algorithm and RISC-V processor. The RISC-V processor is uniquely crafted in three distinct architectures, namely Single-Cycle, Multi-Cycle, and Pipeline.

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