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Proposal: Open Research Institute to build a board for Phase 4 Ground

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Jan Schiefer edited this page Jul 27, 2018 · 9 revisions

Background

An online discussion in the phase4ground Slack raised the possibility of creating an adapter board that would allow us to connect an Analog Devices AD-FMCOMMS2/3/4-EBZ board to an Avnet ultra96 processor board. This would provide a quality radio interface to the ultra96 and create a quite powerful SDR radio. An alternative approach might be to create a mezzanine board for the ultra96, directly using the AD 9361/9364 chips, rather than using the FMCOMMS development boards. This is likely to be much more difficult, though, given that it would be a wideband RF design, rather than just connecting some moderate speed digital signals.

Throughout this document, we will use the AD-FMCOMMS2-EBZ board as an example. The AD-FMCOMMS3-EBZ and AD-FMCOMMS4-EBZ have identical external pin-out, so a solution for one of them should work for any. We will refer to the boards generically as "FMCOMMS board". The AD-FMCOMMS2-EBZ board is described in more detail here.

The proposed board is a mezzanine according to the 96Boards standard. The function of the board is basically to add an FMC port to the Ultra96 development board, (schematic) Initial discussions with 96Boards indicated that as yet, no one else is working on this and that our effort would be welcome and appreciated.

The parasdr board for the Parallella is a very similar design conceptually, and may be valuable to study.

Implementation

FMCOMMS considerations

The standard for FMC is described here. Note that it is not necessary to implement the complete FMC standard, but only the subset required to support the FMCOMMS board.

The pin-out of the FMC connector can be found on sheet 3 of the FMCOMMS schematic. The AD9361 chip can be operated either with a single-ended or a differential interface, both for ADC and DAC. As detailed in the data sheet, there are:

  • 6 differential or 12 single-ended inputs for the receiver ADCs
  • 4 differential outputs for the transmitter DACs
  • SPI for control of the device
  • Miscellaneous control and clock lines.

We need to understand the trade-offs between implementing a single-ended interface or a differential interface for the chip. Differential is most likely to be preferred from a performance point of view, if it can indeed be implemented.

The lowest I/O voltage that the FMCOMMS board can operate is 1.8 V.

ultra96 Considerations

The ultra96 board was announced in March 2018, so documentation is still beginning to materialize. There is documentation in the 96 boards git repo, also the Ultra96 forum on zedboard.org is a good source of information. Supposedly the ultra96 complies with the 96Boards Consumer Edition Specification, but I would take that with a grain of salt. The most notable difference is that the HS connector on the ultra96 is 1.2 V I/O standard, whereas the specification requires 1.8 V. Not really sure how useful this is, also the recommendations for Mezzanine boards are rather loose.

There are 2 major I/O connectors on the Ultra96: The HS connector and the LS connector (J7). I went through the pinout on the schematic, to figure out where each signal goes (this could do with some review). Let's take a closer look at these connectors.

The HS Connector (J3)

The High-Speed (HS) connector mostly connects to Bank 65 of the MPSoC, which is an HP bank with a VCCO of 1.2 V. This means that all these signals are 1.2 V I/O! A fair number of LVDS-capable pins are available, also a good mix of clocking capabilities. As these signals are billed in the schematic as differential pairs, one would hope that the layout designer paid attention to trace lengths, to make sure that P and N signals arrive at their respective pins at the same time.

"But how do you do LVDS with 1.2 V I/O??" you ask. Excellent question, we will discuss this below.

Here are the gory details. The Zynq Ultrascale+ MPSoC Technical Reference Manual is your friend!

HS connector Signal name Bank Zynq pin Bank / Pair Clock Notes
1 MIO11_SPI1_MOSI 500 W2
2 CSI0_C_P 65 N2 65 / 6 QBC
3 NC n/a
4 CSI0_C_N 65 P1
5 NC n/a
6 GND n/a
7 MIO9_SPI1_CS 500 V5
8 CSI0_D0_P 65 N5 65 / 7
9 MIO6_SPI1_SCLK 500 Y1
10 CSI0_D0_N 65 N4
11 MIO10_SPI1_MISO 500 AA2
12 GND n/a
13 GND n/a
14 CSI0_D1_P 65 M2 65 / 8
15 CSI0_MCLK 26 E8 26 / 1 HDGC
16 CSI0_D1_N 65 M1
17 CSI1_MCLK 26 D8
18 GND n/a
19 GND n/a
20 CSI0_D2_P 65 M5 65 / 9 QBC
21 DSI_CLK_P 65 J5 65 / 1 QBC
22 CSI0_D2_N 65 M4
23 DSI_CLK_N 65 H5
24 GND n/a
25 GND n/a
26 CSI0_D3_P 65 L2 65 / 10 GC
27 DSI_D0_P 65 G1 65 / 2 DBC
28 CSI0_D3_N 65 L1
29 DSI_D0_N 65 F1
30 GND n/a
31 GND n/a
32 HSEXP_T2C2_SCL n/a n/a
33 DSI_D1_P 65 E4 65 / 3
34 HSEXP_T2C2_SDA n/a n/a
35 DSI_D1_N 65 E3
36 HSEXP_T2C3_SCL n/a n/a
37 GND n/a
38 HSEXP_T2C3_SDA n/a n/a
39 DSI_D2_P 65 E1 65 / 4
40 GND n/a
41 DSI_D2_N 65 D1
42 CSI1_D0_P 65 P3 65 / 11
43 GND n/a
44 CSI1_D0_N 65 R3
45 DSI_D3_P 65 D3 65 / 5 DBC
46 GND n/a
47 DSI_D3_N 65 C3
48 CSI1_D1_P 65 U2 65 / 12
49 GND n/a
50 CSI1_D1_N 65 U1
51 USB2D3_P n/a n/a
52 GND n/a
53 USB2D3_N n/a n/a
54 CSI1_C_P 65 T3 65 / 13 DBC
55 GND n/a
56 CSI1_C_N 65 T2
57 HSIC_STR 66 A2
58 GND n/a
59 HSIC_DATA 65 C2
60 VCC_PSAUX n/a 1.80 V

The LS Connector (J7)

The LS connector mostly (apart from a bunch of MIO pins) goes to Bank 26, which is an HD bank with a VCCO of 1.8 V. This does seem a bit more useful in order to talk to our FMCOMMS board without level conversion. But while the connector contains several I/O pins that are suitable for differential use, it is probably not safe to assume that these have matched trace lengths. Some investigation is definitely required here!

Here's the details:

LS Connector Signal name Bank Zynq pin Partner Bank / Pair Clock Notes
1 GND n/a
2 GND n/a
3 HD_GPIO_0 26 D7 D6 26 / 2 HDGC
4 POWER_PB_B n/a
5 HD_GPIO_1 26 F8 F7 26 / 3
6 PS_POR_PB_B n/a
7 HD_GPIO_2 26 F7 F8 26 / 3
8 MIO38_SPI0_SCLK 501 C9 n/a
9 HD_GPIO_3 26 G7 F6 26 / 4
10 MIO42_SPI0_MISO 501 D12 n/a
11 HD_GPIO_4 26 F6 G7 26 / 4
12 MIO41_SPI0_CS 501 B10 n/a
13 HD_GPIO_5 26 G5 G6 26 / 5
14 MIO43_SPI0_MOSI 501 E13 n/a
15 LSEXP_I2C0_SDA n/a
16 HD_GPIO_9 26 E6 E5 26 / 7
17 LSEXP_I2C0_SCL n/a
18 HD_GPIO_10 26 E5 E6 26 / 7
19 LSEXP_I2C1_SDA n/a
20 HD_GPIO_11 26 D6 D7 26 / 2 HDGC
21 LSEXP_I2C1_SCL n/a
22 HD_GPIO_12 26 D5 C5 26 / 8 HDGC
23 MIO36_PS_GPIO1_0 501 D10 n/a
24 MIO37_PS_GPIO1_1 501 E11 n/a
25 MIO39_PS_GPIO1_2 501 C10 n/a
26 MIO40_PS_GPIO1_3 501 D11 n/a
27 MIO44_PS_GPIO1_4 501 B11 n/a
28 MIO45_PS_GPIO1_5 501 A11 n/a
29 HD_GPIO_6 26 A6 B6 26 / 6
30 HD_GPIO_13 26 C7 n/a
31 HD_GPIO_7 26 A7 n/a
32 HD_GPIO_14 26 B6 A6 26 / 6
33 HD_GPIO_8 26 G6 G5 26 / 5
34 HD_GPIO_15 26 C5 D5 26 / 8 HDGC
35 VCC_PSAUX n/a 1.80 V
36 VSYS_IN n/a
37 VCC_5V0 n/a 5.00 V
38 VSYS_IN n/a
39 GND n/a
40 GND n/a

Dealing with LVDS in HP Banks

A fundamental difficulty here is that the FMCOMMS board expects mostly 1.8 V LVDS signals, which we cannot provide on the HS connector, as we are connected to a bank with 1.2 V VCCO! One potential solution to this problem could be to use signals from the LS connector for transmit to the FMCOMMS board, and use a trick to interface 1.2 V differential receivers on the HS connector to receive data from the FMCOMMS board, which, according to Xilinx, is possible in certain circumstances.

This is definitely where more research is required. I have found some links in Xilinx documentation that give advice on using LVDS in an HP bank:

If we cannot figure this out or it seems to risky, a level shifter such as the MAX9173 may provide a solution.

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