Initial commit

.github/workflows/build-ubuntu.yml

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+name: RISC-V Arch Tests
+
+on:
+  push:
+    branches: [ main ]
+  pull_request:
+    branches: [ main ]
+
+jobs:
+  setup:
+    runs-on: ubuntu-20.04
+
+    steps:
+      - name: Checkout code
+        uses: actions/checkout@v4
+        with:
+          submodules: 'true'
+
+      - name: Install OSS-CAD-Suite
+        uses: YosysHQ/setup-oss-cad-suite@v3
+
+      - name: Setup Python 3.6
+        uses: actions/setup-python@v5
+        with:
+          python-version: '3.6.7'
+
+      - name: Cache RISC-V GNU Toolchain
+        id: cache-riscv-gnu-toolchain
+        uses: actions/cache@v4
+        with:
+          path: ~/riscv-toolchain
+          key: riscv64-elf-ubuntu-20.04-gcc-nightly-2024.04.12
+
+      - name: Create and activate Python virtual environment
+        run: |
+          python -m venv venv
+          source venv/bin/activate
+          pip install --upgrade pip
+
+      - name: Install RISCOF
+        run: |
+          source venv/bin/activate
+          pip install git+https://github.com/riscv/riscof.git
+
+      - name: Cache Architecture Tests
+        id: cache-arch-tests
+        uses: actions/cache@v4
+        with:
+          path: ~/riscv-arch-tests
+          key: riscv-arch-tests-RV64I
+
+      - name: Install Test Suite
+        if: steps.cache-arch-tests.cache-hit != 'true'
+        run: |
+          source venv/bin/activate
+          riscof --verbose info arch-test --clone
+          sed -i '158s/TEST_JALR_OP(x7, x0, x4, -0x401, x6, 48,0)/TEST_JALR_OP(x7, x1, x4, -0x401, x6, 48,0)/' riscv-arch-test/riscv-test-suite/rv64i_m/I/src/jalr-01.S
+
+      - name: Install RISC-V GNU Toolchain
+        if: steps.cache-riscv-gnu-toolchain.outputs.cache-hit != 'true'
+        run: |
+          wget -nv https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv64-elf-ubuntu-20.04-gcc-nightly-2024.04.12-nightly.tar.gz -P ~/riscv-toolchain
+          mkdir -p ${{ github.workspace }}/rv64-gcc
+          tar -xzf ~/riscv-toolchain/riscv64-elf-ubuntu-20.04-gcc-nightly-2024.04.12-nightly.tar.gz -C ${{ github.workspace }}/rv64-gcc
+          ${{ github.workspace }}/rv64-gcc/riscv/bin/riscv64-unknown-elf-gcc --version
+
+      - name: Install Sail RISC-V Emulator
+        run: |
+          mkdir -p c_emulator/
+          tar -xzvf bin/riscv_sim_RV64.tar.gz -C c_emulator/ riscv_sim_RV64
+          echo "TODO - Gather bare minimum binaries for c_emulator/riscv_sim_RV64 on x64 Ubuntu 20.04 and install into ${{ github.workspace }}"
+
+      - name: Verify Dependency Installations
+        run: |
+          export PATH=$PATH:${{ github.workspace }}/rv64-gcc/riscv/bin:${{ github.workspace }}/c_emulator/riscv_sim_RV64
+          source venv/bin/activate
+          verilator --version
+          riscv64-unknown-elf-gcc --version
+          riscof --version
+
+      - name: Run RISC-V Architectural Tests
+        run: |
+          export PATH=$PATH:${{ github.workspace }}/rv64-gcc/riscv/bin:${{ github.workspace }}/c_emulator
+          source venv/bin/activate
+          riscof run --no-browser --config=config.ini --suite=${{ github.workspace }}/riscv-arch-test/riscv-test-suite/ --env=${{ github.workspace }}/riscv-arch-test/riscv-test-suite/env
+          
+      - name: Logs
+        if: failure()
+        run: |  
+          tree riscof_work/
+          less riscof_work/rv64i_m/I/src/add-01.S/ref/add-01.log
+          echo "MAKEFILE:"
+          less /home/runner/work/rv64_rough/rv64_rough/riscof_work/Makefile.Reference-sail_c_simulator

.github/workflows/lint.yml

@@ -0,0 +1,24 @@
+name: Lint
+
+on:
+  push:
+    branches: [ main ]
+  pull_request:
+    branches: [ main ]
+
+jobs:
+  build:
+    runs-on: ubuntu-20.04
+
+    steps:
+    - name: Checkout code
+      uses: actions/checkout@v4
+      with:
+        submodules: 'true'
+
+    - name: Install OSS-CAD-Suite
+      uses: YosysHQ/setup-oss-cad-suite@v3
+
+    - name: Run Verilator Lint
+      run: |
+        make lint  

.gitignore

@@ -0,0 +1,12 @@
+results/
+obj_dir/
+sim/log.txt
+sim/main.elf
+sim/main.hex
+sim/tmp.bin
+sim/DUT-Lucid64.signature
+plugin-sail_cSim/__pycache__/
+plugin-Lucid64/__pycache__/
+riscof_work/
+sim/output.vcd
+sim/tmp_reversed.bin

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "src"]
+	path = src
+	url = https://github.com/Peter-Herrmann/Lucid64

Makefile

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+SHELL := /bin/bash
+
+VERILATOR = verilator
+VERILATOR_FLAGS = --language 1364-2005 --lint-only -Wall -Isrc/
+
+YOSYS = yosys
+YOSYS_FLAGS = -p "synth -flatten; write_verilog"
+
+DIRECTORIES = src
+VERILOG_SOURCES = $(shell find $(DIRECTORIES) -name '*.v')
+
+# Define colors
+RED = \033[1;31m
+GREEN = \033[1;32m
+BLUE = \033[1;34m
+NC = \033[0m # No Color
+
+.PHONY: all lint synth always 
+
+all: lint synth finish
+
+lint: 
+	@printf "\n${BLUE}%79s${NC}\n\n" "======================== Linting With Verilator ========================"
+	@$(MAKE) -s $(VERILOG_SOURCES:%=%.lint)
+
+synth: 
+	@printf "\n${BLUE}%79s${NC}\n\n" "======================= Synthesizing with Yosys ========================"
+	@$(MAKE) -s $(VERILOG_SOURCES:%=results/synth/%.synth.log)
+
+%.lint: %
+	@printf "Linting %-47s" "$<"
+	@{ $(VERILATOR) $(VERILATOR_FLAGS) $< > /dev/null 2>&1 && printf "${GREEN}%10s${NC}\n" "PASSED"; } \
+	|| { printf "${RED}%10s${NC}\n" "FAILED" && $(VERILATOR) $(VERILATOR_FLAGS) $<; }
+
+results/synth/%.synth.log: % always
+	@mkdir -p $(dir $@)
+	@printf "Synthesizing %-41s" "$<"
+	@{ $(YOSYS) $(YOSYS_FLAGS) $< > $@ 2>&1 && ! grep -i -e warning -e error $@ > /dev/null && printf "${GREEN}%10s${NC}\n" "PASSED"; } \
+	|| { printf "${RED}%10s${NC}\n" "FAILED" && grep -B 1 -i -e warning -e error $@; }
+
+always: ;
+
+finish: always
+	@echo ""

config.ini

@@ -0,0 +1,14 @@
+[RISCOF]
+ReferencePlugin=sail_cSim
+ReferencePluginPath=./plugin-sail_cSim
+DUTPlugin=Lucid64
+DUTPluginPath=./plugin-Lucid64
+
+[Lucid64]
+pluginpath=./plugin-Lucid64
+ispec=./plugin-Lucid64/Lucid64_isa.yaml
+pspec=./plugin-Lucid64/Lucid64_platform.yaml
+target_run=1
+
+[sail_cSim]
+pluginpath=./plugin-sail_cSim

gtkwave/alu_a_src.gtkw

@@ -0,0 +1,4 @@
+00 RS1
+01 U-IMMED
+10 J-IMMED
+11 B-IMMED

gtkwave/alu_b_src.gtkw

@@ -0,0 +1,4 @@
+00 RS2
+01 I-IMMED
+10 S-IMMED
+11 PC

gtkwave/alu_ops.gtkw

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+00000 ADD
+00010 SLL
+00100 SLT
+00110 SLTU
+01000 XOR
+01010 SRL
+01100 OR
+01110 AND
+10000 SUB
+11010 SRA
+11110 PASS
+00001 ADDW
+00011 SLLW
+01011 SRLW
+10001 SUBW
+11011 SRAW

gtkwave/alu_ops_1h.gtkwave

@@ -0,0 +1,16 @@
+0000000000000001 ADD
+0000000000000010 SLL
+0000000000000100 SLT
+0000000000001000 SLTU
+0000000000010000 XOR
+0000000000100000 SRL
+0000000001000000 OR
+0000000010000000 AND
+0000000100000000 SUB
+0000001000000000 SRA
+0000010000000000 PASS
+0000100000000000 ADDW
+0001000000000000 SLLW
+0010000000000000 SRLW
+0100000000000000 SUBW
+1000000000000000 SRAW

gtkwave/branch_cond.gtkw

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+000 BEQ
+001 BNE
+100 BLT
+101 BGE
+110 BLTU
+111 BGEU

gtkwave/branch_cond_1h.gtkw

@@ -0,0 +1,6 @@
+000001 BEQ
+000010 BNE
+000100 BLT
+001000 BGE
+010000 BLTU
+100000 BGEU

gtkwave/mem_width.gtkw

@@ -0,0 +1,4 @@
+00 BYTE
+01 HALF
+10 WORD
+11 DOUBLE

gtkwave/mem_width_1h.gtkw

@@ -0,0 +1,4 @@
+0001 BYTE
+0010 HALF
+0100 WORD
+1000 DOUBLE

gtkwave/opcodes.gtkw

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+0110111 LUI
+0010111 AUIPC
+1101111 JAL
+1100111 JALR
+1100011 BRANCH
+0000011 LOAD
+0100011 STORE
+0010011 OP_IMM
+0110011 OP
+1110011 SYSTEM

gtkwave/opcodes_1h.gtkwave

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+0000000001 LUI
+0000000010 AUIPC
+0000000100 JAL
+0000001000 JALR
+0000010000 BRANCH
+0000100000 LOAD
+0001000000 STORE
+0010000000 OP_IMM
+0100000000 OP
+1000000000 SYSTEM

gtkwave/pc_src.gtkw

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+0 NO_BRANCH
+1 BRANCH

gtkwave/register_names.gtkw

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+0 zero
+1 ra
+2 sp
+3 gp
+4 tp
+5 t0
+6 t1
+7 t2
+8 s0
+9 s1
+10 a0
+11 a1
+12 a2
+13 a3
+14 a4
+15 a5
+16 a6
+17 a7
+18 s2
+19 s3
+20 s4
+21 s5
+22 s6
+23 s7
+24 s8
+25 s9
+26 s10
+27 s11
+28 t3
+29 t4
+30 t5
+31 t6

plugin-Lucid64/Lucid64_isa.yaml

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+Vendor: Peter-Herrmann
+Device: Lucid64
+
+hart_ids: [0]
+hart0:
+  ISA: RV64I
+  physical_addr_sz: 56
+  User_Spec_Version: '2.3'
+  supported_xlen: [64]
+  hw_data_misaligned_support: false
+

plugin-Lucid64/Lucid64_platform.yaml

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+mtime:
+  implemented: true
+  address: 0xbff8
+mtimecmp:
+  implemented: true
+  address: 0x4000
+nmi:
+  label: nmi_vector
+reset:
+  label: reset_vector

plugin-Lucid64/env/link.ld

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+OUTPUT_ARCH( "riscv" )
+ENTRY(rvtest_entry_point)
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text.init : { *(.text.init) }
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+  . = ALIGN(0x1000);
+  .data : { *(.data) }
+  .data.string : { *(.data.string)}
+  .bss : { *(.bss) }
+  _end = .;
+}
+