[WIP] 32 bit support

CMakeLists.txt

@@ -50,8 +50,8 @@ FetchContent_Declare(
 FetchContent_Declare(
   capstone-lib
   GIT_REPOSITORY https://github.com/UoB-HPC/capstone.git
-  GIT_TAG next
-  GIT_PROGRESS TRUE
+  GIT_TAG        next
+  GIT_PROGRESS   TRUE
 
   # Old Git tag pre-Armv9.2
   # GIT_TAG e7be7d99e718ef9741026b80fc6f5e100fdf4f94 # trunk

Makefile

@@ -0,0 +1,33 @@
+# Helper setup to build simeng binary
+
+NPROC ?= 4
+CMAKE ?= /data/tools/cmake/cmake-3.21.0-linux-x86_64/bin/cmake
+BUILD_DIR ?= build
+TYPE ?= Debug
+INSTALLDIR ?= $(shell pwd)/install
+TEST_FLAG ?= OFF
+SST_FLAG ?= ON
+SST_CORE_INSTALLDIR ?= $(SST_CORE_HOME)
+
+all: configure build install
+
+configure: clean
+	$(CMAKE) -B $(BUILD_DIR) -S . -DCMAKE_BUILD_TYPE=$(TYPE) -DCMAKE_INSTALL_PREFIX=$(INSTALLDIR) -DSIMENG_ENABLE_TESTS=$(TEST_FLAG) -DSIMENG_USE_EXTERNAL_LLVM=ON -DSIMENG_ENABLE_SST=$(SST_FLAG) -DSST_INSTALL_DIR=$(SST_CORE_INSTALLDIR) -DLLVM_DIR=/usr/lib/llvm-12/lib/
+
+build:
+	$(CMAKE) --build $(BUILD_DIR) -j $(NPROC)
+
+test:
+	$(CMAKE) --build $(BUILD_DIR) -j $(NPROC) --target test
+
+install:
+	$(CMAKE) --build $(BUILD_DIR) -j $(NPROC) --target install
+
+run_sst_example:
+	sst sst/config/eacf_int_example_config.py
+
+clean:
+	rm -rf build
+
+#.PHONY : all configure build test install run_sst_example clean
+.PHONY : *

README_RV32.md

@@ -0,0 +1,31 @@
+# SimEng Updates to support 32-bit RISC-V ISA
+
+- Added 32-bit RISC-V Architecture support
+  - Sample implementation of how a 32 bit mode can be supported as a configuration. The necessary updates to Architecture, Instruction decode and Instruction execution is added.
+  - Added a Demo yaml file DEMO_RISCV32.yaml that can be used as a reference for running using the emulation core.
+  - The exception handler is updated to process a 32-bit register value for only 4 system calls that where used for internal benchmarks but will need wider adoption accross all other system calls.
+- Added Compressed (16-bit) ISA support
+- Added Instruction trace generation support that can be used to log commited instructions. 
+- 32-bit CSR support
+  - Added few CSRs that and sample implementation on how to use them.
+- Added an alternative implementation of pipeline buffer with variable latency support. 
+  - Supports 0 delay that is benefitial for merging pipeline stages if required.
+  - Supports more than 1 cycle delay between pipeline stages.
+
+# SimEng Update to share the sample implementation of the MicroController (MCU) class core model using 32-bit RISC-V ISA
+- Small MCU like three stage pipeline core model
+- Additonal fixed memory support for LSU in the mcu core
+- Some update to ELF loader and SST image loading to SST memory
+- Makefile to build and run
+- Added support for memory mapped system registers,
+- Used to add a HostTargetInterface for I/O and termination so that spike binaries can run on SimEng
+- Added interrupt support;
+- Fixed csrc handling;
+- Fixed 32-bit sltiu instruction;
+- Fixed 32-bit mulh, mulhu and mulhsu instructions
+- Add support for interrupt by flushing the pipe at execution stage when an interrupt is visible, fix iteration count being int in main.cc
+- Some bug fixes
+
+# Capstone change required for RV32 compresses instruction usage in file include/capstone/capstone.h
+CS_MODE_RISV32GC = CS_MODE_RISCV32 | CS_MODE_RISCVC, ///< RISCV RV32GC
+- 

configs/DEMO_RISCV.yaml

@@ -5,9 +5,10 @@
 
 Core:
   ISA: rv64
-  Simulation-Mode: outoforder
+  Simulation-Mode: emulation
   Clock-Frequency: 2.5
   Fetch-Block-Size: 32
+  Trace: True
 Fetch:
   Fetch-Block-Size: 32
   Loop-Buffer-Size: 0
@@ -36,7 +37,7 @@ Branch-Predictor:
   Branch-Predictor:
   BTB-bitlength: 16
 L1-Data-Memory:
-  Interface-Type: Fixed
+  Interface-Type: Flat
 L1-Instruction-Memory:
   Interface-Type: Flat
 LSQ-L1-Interface:

configs/DEMO_RISCV32.yaml

@@ -0,0 +1,142 @@
+---
+# This file is based off of the current tx2.yaml config and serves as an example configuration for RISC-V cores.
+# The following resources where utilised to create the config file and naming schemes:
+# https://en.wikichip.org/wiki/cavium/microarchitectures/vulcan
+
+Core:
+  ISA: rv32
+  Simulation-Mode: emulation
+  Trace: True
+  Clock-Frequency: 2.5
+  Fetch-Block-Size: 32
+Fetch:
+  Fetch-Block-Size: 32
+  Loop-Buffer-Size: 0
+  Loop-Detection-Threshold: 0
+Process-Image:
+  Heap-Size: 1073741824
+  Stack-Size: 1048576
+Register-Set:
+  GeneralPurpose-Count: 154
+  FloatingPoint-Count: 90
+Pipeline-Widths:
+  Commit: 4
+  Dispatch-Rate: 4
+  FrontEnd: 4
+  LSQ-Completion: 2
+Queue-Sizes:
+  ROB: 180
+  Load: 64
+  Store: 36
+Branch-Predictor:
+  BTB-Tag-Bits: 11
+  Saturating-Count-Bits: 2
+  Global-History-Length: 10
+  RAS-entries: 1
+  Fallback-Static-Predictor: "Always-Taken"
+  Branch-Predictor:
+  BTB-bitlength: 16
+L1-Data-Memory:
+  Interface-Type: Flat
+L1-Instruction-Memory:
+  Interface-Type: Flat
+LSQ-L1-Interface:
+  Access-Latency: 4
+  Exclusive: False
+  Load-Bandwidth: 32
+  Store-Bandwidth: 16
+  Permitted-Requests-Per-Cycle: 2
+  Permitted-Loads-Per-Cycle: 2
+  Permitted-Stores-Per-Cycle: 1
+Ports:
+  0:
+    Portname: Port 0
+    Instruction-Support:
+      - INT_SIMPLE
+      - INT_MUL
+  1:
+    Portname: Port 1
+    Instruction-Support:
+      - INT
+  2:
+    Portname: Port 2
+    Instruction-Support:
+      - INT_SIMPLE
+      - INT_MUL
+      - BRANCH
+  3:
+    Portname: Port 4
+    Instruction-Support:
+      - LOAD
+  4:
+    Portname: Port 5
+    Instruction-Support:
+      - LOAD
+  5:
+    Portname: Port 3
+    Instruction-Support:
+      - STORE
+Reservation-Stations:
+  0:
+    Size: 60
+    Dispatch-Rate: 4
+    Ports:
+      - Port 0
+      - Port 1
+      - Port 2
+      - Port 4
+      - Port 5
+      - Port 3
+Execution-Units:
+  0:
+    Pipelined: True
+  1:
+    Pipelined: True
+  2:
+    Pipelined: True
+  3:
+    Pipelined: True
+  4:
+    Pipelined: True
+  5:
+    Pipelined: True
+Latencies:
+  0:
+    Instruction-Groups:
+      - INT_SIMPLE_ARTH
+      - INT_SIMPLE_LOGICAL
+    Execution-Latency: 1
+    Execution-Throughput: 1
+  1:
+    Instruction-Groups:
+      - INT_MUL
+    Execution-Latency: 5
+    Execution-Throughput: 1
+  2:
+    Instruction-Groups:
+      - INT_DIV
+    Execution-Latency: 39
+    Execution-Throughput: 39
+# CPU-Info mainly used to generate a replica of the special (or system) file directory
+# structure
+CPU-Info:
+  # Set Generate-Special-Dir to 'T' to generate the special files directory, or to 'F' to not.
+  # (Not generating the special files directory may require the user to copy over files manually)
+  Generate-Special-Dir: true
+  # Core-Count MUST be 1 as multi-core is not supported at this time. (TX2 true value is 32)
+  Core-Count: 1
+  # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (TX2 true value is 2)
+  Socket-Count: 1
+  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (TX2 true value is 4)
+  SMT: 1
+  # Below are the values needed to generate /proc/cpuinfo
+  BogoMIPS: 400.00
+  Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid asimdrdm
+  CPU-Implementer: "0x43"
+  CPU-Architecture: 8
+  CPU-Variant: "0x1"
+  CPU-Part: "0x0af"
+  CPU-Revision: 2
+  # Package-Count is used to generate
+  # /sys/devices/system/cpu/cpu{0..Core-Count}/topology/{physical_package_id, core_id}
+  Package-Count: 1

configs/DEMO_RISCV32_mcu.yaml

@@ -0,0 +1,145 @@
+---
+# The following resources where utilised to create the config file and naming schemes:
+# https://en.wikichip.org/wiki/cavium/microarchitectures/vulcan
+
+Core:
+  ISA: rv32
+  Simulation-Mode: mcu
+  Clock-Frequency: 2.5
+  Fetch-Block-Size: 32
+  Trace: True
+  EnableHaltCheck: True
+  MaxStallCycleTimeout: 10000
+  MaxSimCycleTimeout: 1000000000
+  MaxInstrTimeout: 1000000000
+Fetch:
+  Fetch-Block-Size: 32
+  Loop-Buffer-Size: 0
+  Loop-Detection-Threshold: 0
+Process-Image:
+  Heap-Size: 1073741824
+  Stack-Size: 1048576
+Register-Set:
+  GeneralPurpose-Count: 32
+  FloatingPoint-Count: 32
+Pipeline-Widths:
+  Commit: 4
+  Dispatch-Rate: 4
+  FrontEnd: 4
+  LSQ-Completion: 2
+Queue-Sizes:
+  ROB: 180
+  Load: 64
+  Store: 36
+Branch-Predictor:
+  BTB-Tag-Bits: 11
+  Saturating-Count-Bits: 2
+  Global-History-Length: 10
+  RAS-entries: 1 # need change; tmp solution: staticPred header file
+  Fallback-Static-Predictor: "Always-Taken"
+  BTB-bitlength: 16
+  Static-Type: "Always-Taken"
+L1-Data-Memory:
+  Interface-Type: Fixed
+L1-Instruction-Memory:
+  Interface-Type: Flat
+LSQ-L1-Interface:
+  Access-Latency: 1
+  Exclusive: False
+  Load-Bandwidth: 32
+  Store-Bandwidth: 16
+  Permitted-Requests-Per-Cycle: 2
+  Permitted-Loads-Per-Cycle: 2
+  Permitted-Stores-Per-Cycle: 1
+Ports:
+  0:
+    Portname: Port 0
+    Instruction-Support:
+      - INT_SIMPLE
+      - INT_MUL
+  1:
+    Portname: Port 1
+    Instruction-Support:
+      - INT
+  2:
+    Portname: Port 2
+    Instruction-Support:
+      - INT_SIMPLE
+      - INT_MUL
+      - BRANCH
+  3:
+    Portname: Port 4
+    Instruction-Support:
+      - LOAD
+  4:
+    Portname: Port 5
+    Instruction-Support:
+      - LOAD
+  5:
+    Portname: Port 3
+    Instruction-Support:
+      - STORE
+Reservation-Stations:
+  0:
+    Size: 60
+    Dispatch-Rate: 4
+    Ports:
+      - Port 0
+      - Port 1
+      - Port 2
+      - Port 4
+      - Port 5
+      - Port 3
+Execution-Units:
+  0:
+    Pipelined: True
+  1:
+    Pipelined: True
+  2:
+    Pipelined: True
+  3:
+    Pipelined: True
+  4:
+    Pipelined: True
+  5:
+    Pipelined: True
+Latencies:
+  0:
+    Instruction-Groups:
+      - INT_SIMPLE_ARTH
+      - INT_SIMPLE_LOGICAL
+    Execution-Latency: 1
+    Execution-Throughput: 1
+  1:
+    Instruction-Groups:
+      - INT_MUL
+    Execution-Latency: 1
+    Execution-Throughput: 1
+  2:
+    Instruction-Groups:
+      - INT_DIV
+    Execution-Latency: 4
+    Execution-Throughput: 4
+# CPU-Info mainly used to generate a replica of the special (or system) file directory
+# structure
+CPU-Info:
+  # Set Generate-Special-Dir to 'T' to generate the special files directory, or to 'F' to not.
+  # (Not generating the special files directory may require the user to copy over files manually)
+  Generate-Special-Dir: true
+  # Core-Count MUST be 1 as multi-core is not supported at this time. (TX2 true value is 32)
+  Core-Count: 1
+  # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (TX2 true value is 2)
+  Socket-Count: 1
+  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (TX2 true value is 4)
+  SMT: 1
+  # Below are the values needed to generate /proc/cpuinfo
+  BogoMIPS: 400.00
+  Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid asimdrdm
+  CPU-Implementer: "0x43"
+  CPU-Architecture: 8
+  CPU-Variant: "0x1"
+  CPU-Part: "0x0af"
+  CPU-Revision: 2
+  # Package-Count is used to generate
+  # /sys/devices/system/cpu/cpu{0..Core-Count}/topology/{physical_package_id, core_id}
+  Package-Count: 1