Tubular Upgrades

SA-1 Speed Test v5.1 also known as Tubular Upgrade is likely to be largest and most painful release since first public release, hence the tubular.

• Added open bus detection against SA-1 version register ($230E), making it either display nothing (--) or the detected value for both SA-1 (high byte) and SNES CPU (low byte).
• Added support for multiple pages, allowing for more specific SA-1 tests without having the need to change or reprogram the ROM. Use the joypad left/right buttons to change page.
• Readjusted screen table to fit more information but stay compact and discrete.
• Speed results now displays five fixed decimal digits (00.00000 MHz). Resolution is 0.9 kHz or 00.00090 MHz. Still allows for measuring up to ~63 MHz speed values.
• Made sure that ROM alignment is correct for specific tests proper speed measurements.
• Added Page 2, which include address boundary tests, MMIO speed tests and SNES DMA tests:
  • Address boundary test:
    • WRAM <-> ROM test that jumps to an odd address.
    • ROM <-> ROM test that jumps to an odd address.
    • WRAM <-> ROM test that runs on a routine with an even (16) amount of bytes and clocks (the other tests are usually 15 bytes big and 15 clocks long). We will call this type of test "16CLK".
    • ROM <-> ROM 16CLK test.
    • WRAM <-> ROM 16CLK but with odd jumps (16CLK-ODD).
    • ROM <-> ROM 16CLK-ODD test.
    • I-RAM <-> I-RAM ODD test.
    • BW-RAM <-> BW-RAM ODD test.
    • I-RAM <-> I-RAM 16CLK test.
    • BWRAM <-> BWRAM 16CLK test.
    • I-RAM <-> I-RAM 16CLK-ODD test.
    • BW-RAM <-> BW-RAM 16CLK-ODD test.
  • MMIO speed test:
    • WRAM <-> ROM with frequent MMIO reads test.
    • SNES DMA against MMIO reads <-> ROM MMIO test.
    • SNES DMA against MMIO writes <-> ROM MMIO test.
    • SNES DMA against MMIO writes (Super MMC version) <-> ROM MMIO test (may freeze some emulators).
  • Fixed DMA I-RAM/BW-RAM test:
    • SNES DMA against fixed I-RAM reads <-> I-RAM test.
    • SNES DMA against fixed I-RAM writes <-> I-RAM test.
    • SNES DMA against fixed BW-RAM reads <-> BW-RAM test.
    • SNES DMA against fixed BW-RAM writes <-> BW-RAM test.
• Added Page 3, with tests against speed of jumping/branching opcodes:
  • BRA opcode:
    • WRAM <-> ROM
    • ROM <-> ROM
    • WRAM <-> I-RAM
  • BRL opcode:
    • WRAM <-> ROM
    • ROM <-> ROM
    • WRAM <-> I-RAM
  • JMP opcode:
    • WRAM <-> ROM
    • ROM <-> ROM
    • WRAM <-> I-RAM
  • JML opcode:
    • WRAM <-> ROM
    • ROM <-> ROM
    • WRAM <-> I-RAM
  • RTS opcode:
    • WRAM <-> ROM
    • ROM <-> ROM
    • WRAM <-> I-RAM
  • RTL opcode:
    • WRAM <-> ROM
    • ROM <-> ROM
    • WRAM <-> I-RAM
  • RTI opcode:
    • WRAM <-> ROM
    • ROM <-> ROM
    • WRAM <-> I-RAM (available on page 4)
• Added Page 4, with emphasis on SA-1 DMA tests. For this version, S-CPU waits on WRAM, SA-1 executes and waits for DMA on ROM and the devices/SA-1 DMA operation mode are variable.
  • DMA ROM -> I-RAM (DMA priority)
  • DMA ROM -> I-RAM (SA-1 priority)
  • DMA ROM -> BW-RAM (DMA priority)
  • DMA ROM -> BW-RAM (SA-1 priority)
  • DMA I-RAM -> BW-RAM (DMA priority)
  • DMA I-RAM -> BW-RAM (SA-1 priority)
  • DMA BW-RAM -> I-RAM (DMA priority)
  • DMA BW-RAM -> I-RAM (SA-1 priority)

Please note that most of the tests present on Page 4 likely breaks on all emulators because of the way SA-1 IRQ and DMA is set up. Unexpected soft locks and broken speed values were found on bsnes, Snes9x and ZSNES.

Super MMC DMA test (Page 2) softlocks bsnes-plus and probably all bsnes 07x versions. I recommend skipping this page if you run though these emulators.

Some emulators may react oddly on the RTI opcode test. The 16 MHz value, however, seems to be correct. The cycle calculation was either made wrong or an external reference makes the cycle counter rise incorrectly.

Outrageous Improvements

• Made the S-CPU, during the SA-1 clock tests, only start checking for done flag though I-RAM after two NMIs (time over) passed. This will likely make the I-RAM tests run a bit faster and react the expected 10 MHz value.
• Made the SA-1 version display the value seen by both S-CPU and SA-1, plus made the code use 24-bit addressing in case an open bus value is returned from the register.

Correct HDMA

• Fixed HDMA bank byte pointing to the wrong place. Fixes "HDMA WRAM" test reducing SA-1 clock speed.

Hardware Experience

• Fixed invalid SNES IRQ/NMI Super MMC hook which made it crash on real hardware.
• Changed DMA transfer from 0x2000 bytes per time to 0x400 per time.

Complete Test

• Uses a better speed measuring algorithm, to count only actual cycles and not internal (which are usually faster).
• Tests under 8 executing HDMA channels.
• Allows measuring up to ~60 MHz speed.
• Measures S-CPU clock speed.
• Error recovering for when a test case failures.
• Shows SA-1/PPU/CPU version information.

To The Public

First public release.