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fixed existing tests
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@parmigggiana
parmigggiana committed Oct 1, 2024
1 parent 163c274 commit 0aeaace
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Showing 10 changed files with 33 additions and 26 deletions.
7 changes: 6 additions & 1 deletion src/peracotta/commons.py
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Original file line number Diff line number Diff line change
Expand Up @@ -255,7 +255,12 @@ def read_file(name: str) -> str:
item.pop("ram-ecc", None)
item.pop("ram-timings", None)

for bank in parse_udevadm(read_file("udevadm.txt")):
try:
udevadm_rams = parse_udevadm(read_file("udevadm.txt"))
except InputFileNotFoundError:
udevadm_rams = []

for bank in udevadm_rams:
for item in tmp:
if item["sn"] == bank["sn"]:
if any([item[k] != bank[k] for k in item]): # they found the same item but they are different, manual review is needed
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2 changes: 1 addition & 1 deletion tests/main_with_gui/test_gui.py
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
@pytest.fixture
def widget(qtbot):
app = QtWidgets.QApplication.instance()
window = GUI(app, CONFIG["TARALLO_TOKEN"])
window = GUI(app)
qtbot.addWidget(window)
return window

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2 changes: 1 addition & 1 deletion tests/new_tests/test_config.py
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Original file line number Diff line number Diff line change
Expand Up @@ -6,4 +6,4 @@


def test_config(mocker: MockerFixture):
mocked_open: Mock = mocker.patch(open)
assert True
8 changes: 4 additions & 4 deletions tests/parsers/test_alecase.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@

from peracotta.parsers import read_decode_dimms, read_dmidecode, read_lscpu, read_lspci_and_glxinfo
from tests.parsers.read_file import read_file
import deepdiff

filedir = "tests/source_files/alecase/"

Expand Down Expand Up @@ -50,7 +51,7 @@ def test_ram():
"model": "CT102464BA160B.C16",
"ram-ecc": "no",
"ram-timings": "11-11-11-28",
"ram-type": "ddr3",
"ram-type": "DDR3",
"sn": "1949761536",
"type": "ram",
"working": "yes",
Expand All @@ -62,16 +63,15 @@ def test_ram():
"model": "CT102464BA160B.C16",
"ram-ecc": "no",
"ram-timings": "11-11-11-28",
"ram-type": "ddr3",
"ram-type": "DDR3",
"sn": "2172780544",
"type": "ram",
"working": "yes",
},
]
output = read_decode_dimms.parse_decode_dimms(read_file(filedir, "dimms.txt"))

assert len(output) == 2, "2 RAM modules are found"
assert output == expect
assert [d in expect for d in output], "The RAM modules are the expected ones"


def test_baseboard():
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6 changes: 3 additions & 3 deletions tests/parsers/test_asdpc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ def test_ram():
expect = [
{
"ram-ecc": "no",
"ram-type": "ddr3",
"ram-type": "DDR3",
"brand": "G Skill Intl",
"capacity-byte": 8589934592,
"frequency-hertz": 1333000000,
Expand All @@ -55,7 +55,7 @@ def test_ram():
},
{
"ram-ecc": "no",
"ram-type": "ddr3",
"ram-type": "DDR3",
"brand": "G Skill Intl",
"capacity-byte": 8589934592,
"frequency-hertz": 1333000000,
Expand All @@ -68,7 +68,7 @@ def test_ram():
output = read_decode_dimms.parse_decode_dimms(read_file(filedir, "dimms.txt"))

assert len(output) == 2, "2 RAM modules are found"
assert output == expect
assert [d in expect for d in output], "The RAM modules are the expected ones"


def test_baseboard():
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2 changes: 1 addition & 1 deletion tests/parsers/test_castes-pc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ def test_ram():
output = read_decode_dimms.parse_decode_dimms(read_file(filedir, "dimms.txt"))

assert len(output) == 2, "2 RAM modules are found"
assert output == expect
assert [d in expect for d in output], "The RAM modules are the expected ones"


def test_baseboard():
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23 changes: 12 additions & 11 deletions tests/parsers/test_dimms.py
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ def test_ecc_ram1():
"sn": "3375612524",
"frequency-hertz": 667000000,
"capacity-byte": 2147483648,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
Expand All @@ -28,14 +28,15 @@ def test_ecc_ram1():
"sn": "3392385900",
"frequency-hertz": 667000000,
"capacity-byte": 2147483648,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
]
output = read_decode_dimms.parse_decode_dimms(read_file(filedir, "ECC/R451-R450.txt"))

assert output == expect
assert len(output) == 2, "There are two RAM modules"
assert [d in expect for d in output], "The RAM modules are the expected ones"


def test_ecc_ram1_not_an_hex():
Expand All @@ -48,7 +49,7 @@ def test_ecc_ram1_not_an_hex():
"sn": "0F00xb4r",
"frequency-hertz": 667000000,
"capacity-byte": 2147483648,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
Expand All @@ -60,7 +61,7 @@ def test_ecc_ram1_not_an_hex():
"sn": "0xCA33B3RC",
"frequency-hertz": 667000000,
"capacity-byte": 2147483648,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
Expand All @@ -79,7 +80,7 @@ def test_ecc_ram2():
"sn": "2853609420",
"frequency-hertz": 667000000,
"capacity-byte": 1073741824,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
Expand All @@ -90,7 +91,7 @@ def test_ecc_ram2():
"sn": "2836829644",
"frequency-hertz": 667000000,
"capacity-byte": 1073741824,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
Expand All @@ -110,7 +111,7 @@ def test_ram1():
"sn": "16416",
"frequency-hertz": 800000000,
"capacity-byte": 1073741824,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "no",
"ram-timings": "6-6-6-18",
},
Expand All @@ -122,7 +123,7 @@ def test_ram1():
"sn": "8224",
"frequency-hertz": 800000000,
"capacity-byte": 1073741824,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "no",
"ram-timings": "6-6-6-18",
},
Expand All @@ -134,7 +135,7 @@ def test_ram1():
"sn": "12320",
"frequency-hertz": 800000000,
"capacity-byte": 1073741824,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "no",
"ram-timings": "6-6-6-18",
},
Expand All @@ -146,7 +147,7 @@ def test_ram1():
"sn": "8225",
"frequency-hertz": 800000000,
"capacity-byte": 1073741824,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "no",
"ram-timings": "6-6-6-18",
},
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3 changes: 2 additions & 1 deletion tests/parsers/test_rottame.py
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Original file line number Diff line number Diff line change
Expand Up @@ -50,12 +50,13 @@ def test_ram():
"sn": "2972574626",
"frequency-hertz": 533000000,
"capacity-byte": 536870912,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "no",
"ram-timings": "5-4-4-12",
}
]
output = read_decode_dimms.parse_decode_dimms(read_file(filedir, "dimms.txt"))
print(output)

assert output == expect

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4 changes: 2 additions & 2 deletions tests/parsers/test_travasato.py
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ def test_ram():
"sn": "3375612238",
"frequency-hertz": 667000000,
"capacity-byte": 2147483648,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
Expand All @@ -62,7 +62,7 @@ def test_ram():
"sn": "3392385358",
"frequency-hertz": 667000000,
"capacity-byte": 2147483648,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
},
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2 changes: 1 addition & 1 deletion tests/parsers/test_viavai.py
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ def test_ram():
"sn": "3072778780",
"frequency-hertz": 667000000,
"capacity-byte": 1073741824,
"ram-type": "ddr2",
"ram-type": "DDR2",
"ram-ecc": "yes",
"ram-timings": "5-5-5-15",
}
Expand Down

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