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lab4
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Yifan Ruan committed Jun 12, 2022
1 parent ae36ba7 commit 162ae04
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Showing 15 changed files with 630 additions and 73 deletions.
2 changes: 1 addition & 1 deletion Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,7 @@ microbench:
./build/emu --diff ./riscv64-nemu-interpreter-so -i ./ready-to-run/challenge/microbench-riscv64-nutshell.bin $(VOPT) || true

test-lab4: sim
TEST=$(TEST) ./build/emu --diff ./riscv64-nemu-interpreter-so -i ./ready-to-run/lab4/all-test-priv.bin $(VOPT) || true
TEST=$(TEST) ./build/emu --no-diff -i ./ready-to-run/lab4/all-test-priv.bin $(VOPT) || true

test-lab4full: sim
TEST=$(TEST) ./build/emu --diff ./riscv64-nemu-interpreter-so -i ./ready-to-run/lab4/all-test-privfull.bin $(VOPT) || true
Expand Down
103 changes: 99 additions & 4 deletions vsrc/include/pipes.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ package pipes;
import common::*;
/* Define instrucion decoding rules here */

/* rv64i + rv64im */
/* rv64i + rv64im + csr */

parameter OP_LUI = 7'b0110111;

Expand Down Expand Up @@ -97,6 +97,18 @@ parameter F3_SRLW = 3'b101;
parameter F3_REMW = 3'b110;
parameter F3_REMUW = 3'b111;

parameter OP_SYSTEM = 7'b1110011;
parameter F3_PRIV = 3'b000;
parameter F25_ECALL = 25'b0000000000000000000000000;
parameter F25_MRET = 25'b0011000000100000000000000;
parameter F3_CSSRW = 3'b001;
parameter F3_CSRRS = 3'b010;
parameter F3_CSRRC = 3'b011;
parameter F3_CSSRWI = 3'b101;
parameter F3_CSRRSI = 3'b110;
parameter F3_CSRRCI = 3'b111;

parameter OP_ZERO = 7'b0000000;

/* Define pipeline structures here */

Expand All @@ -117,13 +129,15 @@ typedef enum logic [4:0] {
ALU_RIGHT6_SEXT,
ALU_RIGHT32,
ALU_RIGHT32_SEXT,
ALU_NEXT_PC
ALU_NEXT_PC,
ALU_AND_REV,
ALU_REV_AND
} alufunc_t;

typedef struct packed {
u32 raw_instr;
u64 pc;
u1 valid;
u1 valid, instr_misalign;
} fetch_data_t;

typedef enum logic [2:0] {
Expand All @@ -132,9 +146,26 @@ typedef enum logic [2:0] {
B,
U,
S,
J
J,
CSR
} decode_op_t;

typedef struct packed {
u1
is_csr,
is_err,
is_mret,
illegal_instr,
instr_misalign,
is_ecall,
load_misalign,
store_misalign,
csra,
csrb;
u64 csrs;
csr_addr_t csr;
} csr_control_t;

typedef struct packed {
u32 raw_instr;
u1 PCSel, RegWEn, BrUn, BSel, ASel, ra1En, ra2En, WBSel, SltEn, EqEn, LTEn, EqSel, LTSel, mem_unsigned, loadEn;
Expand All @@ -145,6 +176,7 @@ typedef struct packed {
u2 multiplyEn; // {W, is}
u4 divideEn; // {W, is, type_rem, unsgn}
creg_addr_t wa;
csr_control_t csr;
} control_t;

typedef struct packed {
Expand All @@ -167,6 +199,69 @@ typedef struct packed {
u1 valid, addr31;
} memory_data_t;

// csrs
parameter u12 CSR_MHARTID = 12'hf14;
parameter u12 CSR_MIE = 12'h304;
parameter u12 CSR_MIP = 12'h344;
parameter u12 CSR_MTVEC = 12'h305;
parameter u12 CSR_MSTATUS = 12'h300;
parameter u12 CSR_MSCRATCH = 12'h340;
parameter u12 CSR_MEPC = 12'h341;
parameter u12 CSR_SATP = 12'h180;
parameter u12 CSR_MCAUSE = 12'h342;
parameter u12 CSR_MCYCLE = 12'hb00;
parameter u12 CSR_MTVAL = 12'h343;

typedef struct packed {
u1 sd;
logic [MXLEN-2-36:0] wpri1;
u2 sxl;
u2 uxl;
u9 wpri2;
u1 tsr;
u1 tw;
u1 tvm;
u1 mxr;
u1 sum;
u1 mprv;
u2 xs;
u2 fs;
u2 mpp;
u2 wpri3;
u1 spp;
u1 mpie;
u1 wpri4;
u1 spie;
u1 upie;
u1 mie;
u1 wpri5;
u1 sie;
u1 uie;
} mstatus_t;

typedef struct packed {
u4 mode;
u16 asid;
u44 ppn;
} satp_t;

typedef struct packed {
u64
mhartid, // Hardware thread Id, read-only as 0 in this work
mie, // Machine interrupt-enable register
mip, // Machine interrupt pending
mtvec; // Machine trap-handler base address
mstatus_t
mstatus; // Machine status register
u64
mscratch, // Scratch register for machine trap handlers
mepc, // Machine exception program counter
satp, // Supervisor address translation and protection, read-only as 0 in this work
mcause, // Machine trap cause
mcycle, // Counter
mtval;
} csr_regs_t;

endpackage

`endif
93 changes: 73 additions & 20 deletions vsrc/pipeline/core.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@
`include "pipeline/writeback/writeback.sv"
`include "pipeline/hazard/hazard.sv"
`include "pipeline/forward/forward.sv"
`include "pipeline/csr/csr.sv"

`else

Expand Down Expand Up @@ -63,11 +64,21 @@ module core
u64 d_pc, imm;
u1 d_valid;

u1 csr_flush, csr_valid;
u64 pc_csr;

csr_addr_t csr_ra, csr_wa;
u64 csr_rd, csr_wd;

u1 is_stall, is_int;

selectpc selectpc(
.pc_address,
.PCSel,
.predPC,
.pc_selected(pc_nxt)
.pc_selected(pc_nxt),
.pc_csr,
.csr_flush
);

pcreg pcreg(
Expand All @@ -84,9 +95,7 @@ module core
.pc,
.dataF_nxt,
.imem_wait,
.predPC,
.clk,
.reset
.predPC
);

freg freg(
Expand All @@ -104,7 +113,8 @@ module core
.ctl,
.d_pc,
.d_valid,
.imm
.imm,
.csr_ra
);

forward forward(
Expand Down Expand Up @@ -133,7 +143,8 @@ module core
.dataD_nxt,
.last_pc(dataF_nxt.pc),
.PCSel,
.pc_address
.pc_address,
.csr_rd
);

hazard hazard(
Expand All @@ -146,7 +157,9 @@ module core
.FWrite,
.DWrite,
.EWrite,
.MWrite
.MWrite,
.csr_flush,
.is_stall
);

dreg dreg(
Expand Down Expand Up @@ -178,7 +191,10 @@ module core
.dreq,
.dataE,
.dataM_nxt,
.dmem_wait
.dmem_wait,
.clk,
.reset,
.csr_flush
);

mreg mreg(
Expand All @@ -193,9 +209,46 @@ module core
.dataM,
.wa,
.wd,
.wvalid
.wvalid,
.csr_wa,
.csr_wd,
.csr_flush,
.csr_valid,
.is_int
);

u64 real_pc;
always_comb begin
if (dataM.pc > 0) begin
real_pc = dataM.pc;
end else if (dataE.pc > 0) begin
real_pc = dataE.pc;
end else if (dataD.pc > 0) begin
real_pc = dataD.pc;
end else if (dataF.pc > 0) begin
real_pc = dataF.pc;
end else begin
real_pc = dataF_nxt.pc;
end
end

csr csr(
.clk,
.reset,
.csr_ra,
.csr_rd,
.csr_wa,
.csr_wd,
.csr_control(dataM.ctl.csr),
.pc_csr,
.trint,
.swint,
.exint,
.csr_valid,
.is_stall,
.is_int,
.real_pc
);

regfile regfile(
.clk, .reset,
Expand All @@ -213,7 +266,7 @@ module core
.clock (clk),
.coreid (0),
.index (0),
.valid (~reset && dataM.valid),
.valid (~reset && dataM.valid && ~is_stall),
.pc (dataM.pc),
.instr (dataM.ctl.raw_instr),
.skip (dataM.ctl.MemRW != 2'b00 && dataM.addr31 == 0),
Expand Down Expand Up @@ -274,21 +327,21 @@ module core
DifftestCSRState DifftestCSRState(
.clock (clk),
.coreid (0),
.priviledgeMode (3),
.mstatus (0),
.sstatus (0 /* mstatus & 64'h800000030001e000 */),
.mepc (0),
.priviledgeMode (csr.mode_nxt[1:0]),
.mstatus (csr.regs_nxt.mstatus),
.sstatus (csr.regs_nxt.mstatus & 64'h800000030001e000),
.mepc (csr.regs_nxt.mepc),
.sepc (0),
.mtval (0),
.mtval (csr.regs_nxt.mtval),
.stval (0),
.mtvec (0),
.mtvec (csr.regs_nxt.mtvec),
.stvec (0),
.mcause (0),
.mcause (csr.regs_nxt.mcause),
.scause (0),
.satp (0),
.mip (0),
.mie (0),
.mscratch (0),
.mip (csr.regs_nxt.mip),
.mie (csr.regs_nxt.mie),
.mscratch (csr.regs_nxt.mscratch),
.sscratch (0),
.mideleg (0),
.medeleg (0)
Expand Down
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