Topology: NHLT: Intel: Add support for blob format v3.0 #276
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plbossart
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Sep 16, 2024
jsarha
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Oct 2, 2024
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jsarha
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Oct 15, 2024
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| blob30->gateway_attributes = blob->gateway_attributes; | ||
| blob30->version = SSP_BLOB_VER_3_0; | ||
| for (i = 0; i < 8; i++) |
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Should maybe use SP_TS_GROUP_SIZE here too (or ARRAY_SIZE(blob->ts_group)).
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Thanks, I fixed it, and also for v1.5! Can you please re-review @jsarha .
This patch adds the 3.0 format that is used for the PTL ACE3.x platform. Blob 3.0 is based on blob 1.5 but it adds DMA control registers settings and has some changes in registers bitfields. This patch also fixes some compile warnings when NHLT_DEBUG is set for comparing int with unsigned in ssp-debug.c for code for all blobs variants. Signed-off-by: Seppo Ingalsuo <[email protected]>
The MOD = 1 is the only allowed setting for SSC0(31) bit for cAVS 2.x and all ACE versions 1.x, 2.x, and 3.x Signed-off-by: Seppo Ingalsuo <[email protected]>
- The SSC1 bits 21 and 20, TSRE and RSRE, do not exist. - The SSC0 bit 30 ACS does not exist. - The SSC0 bit 6 ECS does not exist but needs to be set, add note. - The MDIVXCTRL bits 20:21 MNDSS does not exist. Signed-off-by: Seppo Ingalsuo <[email protected]>
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kv2019i
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The MOD = 1 is the only allowed setting for SSC0(31) bit for cAVS 2.x and all ACE versions 1.x, 2.x, and 3.x Closes: #276 Signed-off-by: Seppo Ingalsuo <[email protected]> Signed-off-by: Jaroslav Kysela <[email protected]>
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- The SSC1 bits 21 and 20, TSRE and RSRE, do not exist. - The SSC0 bit 30 ACS does not exist. - The SSC0 bit 6 ECS does not exist but needs to be set, add note. - The MDIVXCTRL bits 20:21 MNDSS does not exist. Closes: #276 Signed-off-by: Seppo Ingalsuo <[email protected]> Signed-off-by: Jaroslav Kysela <[email protected]>
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