Merge branch '2021-09-30-whitespace-cleanups' into next

- A large number of whitespace cleanups from Wolfgang

Licenses/lgpl-2.0.txt

@@ -133,7 +133,7 @@ such a program is covered only if its contents constitute a work based
 on the Library (independent of the use of the Library in a tool for
 writing it).  Whether that is true depends on what the Library does
 and what the program that uses the Library does.
-  
+
   1. You may copy and distribute verbatim copies of the Library's
 complete source code as you receive it, in any medium, provided that
 you conspicuously and appropriately publish on each copy an

Makefile

@@ -327,14 +327,14 @@ os_x_before	= $(shell if [ $(DARWIN_MAJOR_VERSION) -le $(1) -a \
 	$(DARWIN_MINOR_VERSION) -le $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
 
 os_x_after = $(shell if [ $(DARWIN_MAJOR_VERSION) -ge $(1) -a \
-	$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)	
+	$(DARWIN_MINOR_VERSION) -ge $(2) ] ; then echo "$(3)"; else echo "$(4)"; fi ;)
 
 # Snow Leopards build environment has no longer restrictions as described above
 HOSTCC       = $(call os_x_before, 10, 5, "cc", "gcc")
 KBUILD_HOSTCFLAGS  += $(call os_x_before, 10, 4, "-traditional-cpp")
 KBUILD_HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress")
 
-# macOS Mojave (10.14.X) 
+# macOS Mojave (10.14.X)
 # Undefined symbols for architecture x86_64: "_PyArg_ParseTuple"
 KBUILD_HOSTLDFLAGS += $(call os_x_after, 10, 14, "-lpython -dynamclib", "")
 endif
@@ -1739,7 +1739,7 @@ endif
 # May be overridden by arch/$(ARCH)/config.mk
 ifdef CONFIG_LTO
 quiet_cmd_u-boot__ ?= LTO     $@
-      cmd_u-boot__ ?= 								\
+      cmd_u-boot__ ?=								\
 		$(CC) -nostdlib -nostartfiles					\
 		$(LTO_FINAL_LDFLAGS) $(c_flags)					\
 		$(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@	\

README

@@ -300,7 +300,6 @@ board_init_r():
 	- loads U-Boot or (in falcon mode) Linux
 
 
-
 Configuration Options:
 ----------------------
 

arch/arc/lib/libgcc2.h

@@ -35,7 +35,7 @@ typedef		 int HItype	__attribute__ ((mode (HI)));
 typedef unsigned int UHItype	__attribute__ ((mode (HI)));
 #if MIN_UNITS_PER_WORD > 1
 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1.  */
-typedef 	 int SItype	__attribute__ ((mode (SI)));
+typedef		 int SItype	__attribute__ ((mode (SI)));
 typedef unsigned int USItype	__attribute__ ((mode (SI)));
 #if __SIZEOF_LONG_LONG__ > 4
 /* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2.  */

arch/arm/cpu/arm926ejs/armada100/timer.c

@@ -45,7 +45,7 @@ struct armd1tmr_registers {
 #define TIMER			0	/* Use TIMER 0 */
 /* Each timer has 3 match registers */
 #define MATCH_CMP(x)		((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 		0xffffffff
+#define TIMER_LOAD_VAL		0xffffffff
 #define	COUNT_RD_REQ		0x1
 
 DECLARE_GLOBAL_DATA_PTR;

arch/arm/cpu/arm926ejs/cache.c

@@ -89,4 +89,3 @@ void enable_caches(void)
 	dcache_enable();
 #endif
 }
-

arch/arm/cpu/armv7/psci-common.c

@@ -43,4 +43,3 @@ u32 __secure psci_get_context_id(int cpu)
 {
 	return psci_context_id[cpu];
 }
-

arch/arm/cpu/armv8/fel_utils.S

@@ -64,18 +64,18 @@ ENTRY(return_to_fel)
 
 /* AArch32 code to restore the state from fel_stash and return back to FEL. */
 back_in_32:
-	.word	0xe59f0028 	// ldr	r0, [pc, #40]	; load fel_stash address
-	.word	0xe5901008 	// ldr	r1, [r0, #8]
-	.word	0xe129f001 	// msr	CPSR_fc, r1
+	.word	0xe59f0028	// ldr	r0, [pc, #40]	; load fel_stash address
+	.word	0xe5901008	// ldr	r1, [r0, #8]
+	.word	0xe129f001	// msr	CPSR_fc, r1
 	.word	0xf57ff06f	// isb
-	.word	0xe590d000 	// ldr	sp, [r0]
-	.word	0xe590e004 	// ldr	lr, [r0, #4]
-	.word	0xe5901010 	// ldr	r1, [r0, #16]
-	.word	0xee0c1f10 	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
-	.word	0xe590100c 	// ldr	r1, [r0, #12]
-	.word	0xee011f10 	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
+	.word	0xe590d000	// ldr	sp, [r0]
+	.word	0xe590e004	// ldr	lr, [r0, #4]
+	.word	0xe5901010	// ldr	r1, [r0, #16]
+	.word	0xee0c1f10	// mcr	15, 0, r1, cr12, cr0, {0} ; VBAR
+	.word	0xe590100c	// ldr	r1, [r0, #12]
+	.word	0xee011f10	// mcr	15, 0, r1, cr1, cr0, {0}  ; SCTLR
 	.word	0xf57ff06f	// isb
-	.word	0xe12fff1e 	// bx	lr		; return to FEL
+	.word	0xe12fff1e	// bx	lr		; return to FEL
 fel_stash_addr:
 	.word   0x00000000	// receives fel_stash addr, by AA64 code above
 ENDPROC(return_to_fel)

arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3

@@ -42,22 +42,22 @@ Flash Layout
    pre-silicon platforms (simulator and emulator):
 
 	-------------------------
-	| 	FIT Image	|
+	|	FIT Image	|
 	| (linux + DTB + RFS)	|
 	------------------------- ----> 0x0120_0000
-	| 	Debug Server FW |
+	|	Debug Server FW |
 	------------------------- ----> 0x00C0_0000
-	|	AIOP FW 	|
+	|	AIOP FW		|
 	------------------------- ----> 0x0070_0000
-	|	MC FW 		|
+	|	MC FW		|
 	------------------------- ----> 0x006C_0000
-	| 	MC DPL Blob 	|
+	|	MC DPL Blob	|
 	------------------------- ----> 0x0020_0000
-	| 	BootLoader + Env|
+	|	BootLoader + Env|
 	------------------------- ----> 0x0000_1000
-	|	PBI 		|
+	|	PBI		|
 	------------------------- ----> 0x0000_0080
-	|	RCW 		|
+	|	RCW		|
 	------------------------- ----> 0x0000_0000
 
 	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
@@ -70,45 +70,45 @@ Flash Layout
 	----------------------------------------- ----> 0x5_8790_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8510_0000	|
-	|	PHY firmware (2M)	 	|			|
+	|	PHY firmware (2M)		|			|
 	----------------------------------------- ----> 0x5_84F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Alt
 	----------------------------------------- ----> 0x5_84D0_0000	| Bank
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
-	|	MC DPC Blob (1M) 		|			|
+	|	MC DPC Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8480_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8470_0000	|
-	| 	MC FW (4M)			|			|
+	|	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8430_0000	|
-	|	BootLoader Environment (1M) 	|			|
+	|	BootLoader Environment (1M)	|			|
 	----------------------------------------- ----> 0x5_8420_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8410_0000	|
-	|	RCW and PBI (1M) 		|			|
+	|	RCW and PBI (1M)		|			|
 	----------------------------------------- ----> 0x5_8400_0000 ---
 	|	.. Unused .. (7M)		|			|
 	----------------------------------------- ----> 0x5_8390_0000	|
 	| FIT Image (linux + DTB + RFS)	(40M)	|			|
 	----------------------------------------- ----> 0x5_8110_0000	|
-	|	PHY firmware (2M)	 	|			|
+	|	PHY firmware (2M)		|			|
 	----------------------------------------- ----> 0x5_80F0_0000	| 64K
 	|	Debug Server FW (2M)		|			| Bank
 	----------------------------------------- ----> 0x5_80D0_0000	|
 	|	AIOP FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
-	|	MC DPC Blob (1M) 		|			|
+	|	MC DPC Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8080_0000	|
 	|	MC DPL Blob (1M)		|			|
 	----------------------------------------- ----> 0x5_8070_0000	|
-	| 	MC FW (4M)			|			|
+	|	MC FW (4M)			|			|
 	----------------------------------------- ----> 0x5_8030_0000	|
-	|	BootLoader Environment (1M) 	|			|
+	|	BootLoader Environment (1M)	|			|
 	----------------------------------------- ----> 0x5_8020_0000	|
 	|	BootLoader (1M)			|			|
 	----------------------------------------- ----> 0x5_8010_0000	|
-	|	RCW and PBI (1M) 		|			|
+	|	RCW and PBI (1M)		|			|
 	----------------------------------------- ----> 0x5_8000_0000 ---
 
 	128-MB NOR flash layout for QDS and RDB boards

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -250,7 +250,7 @@ ENTRY(lowlevel_init)
 	 * b. We use only Region0 whose NSAID write/read is EN
 	 *
 	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
-	 * 	 placeholders.
+	 *	 placeholders.
 	 */
 
 .macro tzasc_prog, xreg
@@ -259,7 +259,7 @@ ENTRY(lowlevel_init)
 	mov     x16, #0x10000
 	mul     x14, \xreg, x16
 	add     x14, x14,x12
-	mov 	x1, #0x8
+	mov	x1, #0x8
 	add     x1, x1, x14
 
 	ldr     w0, [x1]		/* Filter 0 Gate Keeper Register */

arch/arm/cpu/armv8/hisilicon/pinmux.c

@@ -181,5 +181,3 @@ int hi6220_pinmux_config(int peripheral)
 
 	return 0;
 }
-
-

arch/arm/cpu/armv8/xen/hypercall.S

@@ -76,4 +76,3 @@ HYPERCALL2(sched_op);
 HYPERCALL2(event_channel_op);
 HYPERCALL2(hvm_op);
 HYPERCALL2(memory_op);
-

arch/arm/dts/sama7g5-pinfunc.h

@@ -921,4 +921,3 @@
 #define PIN_PE7__TIOA4			PINMUX_PIN(PIN_PE7, 3, 3)
 #define PIN_PE7__ISC_D11		PINMUX_PIN(PIN_PE7, 5, 2)
 #define PIN_PE7__G1_TSUCOMP		PINMUX_PIN(PIN_PE7, 7, 1)
-

arch/arm/dts/vf610-pinfunc.h

@@ -424,7 +424,7 @@
 #define VF610_PAD_PTD29__FTM3_CH2		0x104 0x000 ALT4 0x0
 #define VF610_PAD_PTD29__DSPI2_SIN		0x104 0x000 ALT5 0x0
 #define VF610_PAD_PTD29__DEBUG_OUT11		0x104 0x000 ALT7 0x0
-#define VF610_PAD_PTD28__GPIO_66	 	0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__GPIO_66		0x108 0x000 ALT0 0x0
 #define VF610_PAD_PTD28__FB_AD28		0x108 0x000 ALT1 0x0
 #define VF610_PAD_PTD28__NF_IO12		0x108 0x000 ALT2 0x0
 #define VF610_PAD_PTD28__I2C2_SCL		0x108 0x34C ALT3 0x1

arch/arm/include/asm/arch-am33xx/cpu.h

@@ -408,7 +408,7 @@ struct cm_dpll {
 	unsigned int resv1;
 	unsigned int clktimer2clk;	/* offset 0x04 */
 	unsigned int resv2[11];
-	unsigned int clkselmacclk;	/* offset 0x34 */ 
+	unsigned int clkselmacclk;	/* offset 0x34 */
 };
 #endif /* CONFIG_AM43XX */
 

arch/arm/include/asm/arch-armada100/mfp.h

@@ -17,7 +17,7 @@
 /*
  * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
  *
- * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ *				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
  */
 /* UART1 */
 #define MFP107_UART1_TXD	(MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)

arch/arm/include/asm/arch-imxrt/imxrt.h

@@ -8,4 +8,3 @@
 #define _ASM_ARCH_IMXRT_H
 
 #endif /* _ASM_ARCH_IMXRT_H */
-

arch/arm/include/asm/arch-mx25/imx-regs.h

@@ -50,11 +50,11 @@ struct ccm_regs {
 
 /* Enhanced SDRAM Controller (ESDRAMC) registers */
 struct esdramc_regs {
-	u32 ctl0; 	/* control 0 */
-	u32 cfg0; 	/* configuration 0 */
-	u32 ctl1; 	/* control 1 */
-	u32 cfg1; 	/* configuration 1 */
-	u32 misc; 	/* miscellaneous */
+	u32 ctl0;	/* control 0 */
+	u32 cfg0;	/* configuration 0 */
+	u32 ctl1;	/* control 1 */
+	u32 cfg1;	/* configuration 1 */
+	u32 misc;	/* miscellaneous */
 	u32 pad[3];
 	u32 cdly1;	/* Delay Line 1 configuration debug */
 	u32 cdly2;	/* delay line 2 configuration debug */
@@ -66,11 +66,11 @@ struct esdramc_regs {
 
 /* General Purpose Timer (GPT) registers */
 struct gpt_regs {
-	u32 ctrl;   	/* control */
-	u32 pre;    	/* prescaler */
-	u32 stat;   	/* status */
-	u32 intr;   	/* interrupt */
-	u32 cmp[3]; 	/* output compare 1-3 */
+	u32 ctrl;	/* control */
+	u32 pre;	/* prescaler */
+	u32 stat;	/* status */
+	u32 intr;	/* interrupt */
+	u32 cmp[3];	/* output compare 1-3 */
 	u32 capt[2];	/* input capture 1-2 */
 	u32 counter;	/* counter */
 };
@@ -456,7 +456,7 @@ struct epit_regs {
 #define GPT_CTRL_TEN		1		/* Timer enable	*/
 
 /* WDOG enable */
-#define WCR_WDE 		0x04
+#define WCR_WDE			0x04
 #define WSR_UNLOCK1		0x5555
 #define WSR_UNLOCK2		0xAAAA
 

arch/arm/include/asm/arch-mx5/imx-regs.h

@@ -43,7 +43,7 @@
 #define MMC_SDHC1_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00008000)
 #define UART3_BASE		(SPBA0_BASE_ADDR + 0x0000C000)
-#define CSPI1_BASE_ADDR 	(SPBA0_BASE_ADDR + 0x00010000)
+#define CSPI1_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00010000)
 #define SSI2_BASE_ADDR		(SPBA0_BASE_ADDR + 0x00014000)
 #define MMC_SDHC3_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00020000)
 #define MMC_SDHC4_BASE_ADDR	(SPBA0_BASE_ADDR + 0x00024000)
@@ -97,7 +97,7 @@
 #define IIM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x00098000)
 #define CSU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x0009C000)
 #define ARM_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A0000)
-#define OWIRE_BASE_ADDR 	(AIPS2_BASE_ADDR + 0x000A4000)
+#define OWIRE_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A4000)
 #define FIRI_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000A8000)
 #define CSPI2_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000AC000)
 #define SDMA_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000B0000)

arch/arm/include/asm/arch-mx6/mx6_plugin.S

@@ -7,10 +7,10 @@
 
 #ifdef CONFIG_ROM_UNIFIED_SECTIONS
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #else
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0xC0
-#define ROM_VERSION_OFFSET               	0x48
+#define ROM_VERSION_OFFSET			0x48
 #endif
 #define ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15	0xC4
 #define ROM_API_TABLE_BASE_ADDR_MX6DL_TO12	0xC4

arch/arm/include/asm/arch-mx7/mx7_plugin.S

@@ -6,7 +6,7 @@
 #include <config.h>
 
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #define ROM_API_HWCNFG_SETUP_OFFSET		0x08
 
 plugin_start:

arch/arm/include/asm/arch-mx7ulp/mx7ulp_plugin.S

@@ -6,7 +6,7 @@
 #include <config.h>
 
 #define ROM_API_TABLE_BASE_ADDR_LEGACY		0x180
-#define ROM_VERSION_OFFSET               	0x80
+#define ROM_VERSION_OFFSET			0x80
 #define ROM_API_HWCNFG_SETUP_OFFSET		0x08
 
 plugin_start:

arch/arm/include/asm/arch-rockchip/cru_rk3368.h

@@ -126,17 +126,17 @@ enum {
 	/* GLB_RST_CON */
 	PMU_GLB_SRST_CTRL_SHIFT		= 2,
 	PMU_GLB_SRST_CTRL_MASK		= GENMASK(3, 2),
-	PMU_RST_BY_FST_GLB_SRST 	= 0,
-	PMU_RST_BY_SND_GLB_SRST 	= 1,
+	PMU_RST_BY_FST_GLB_SRST		= 0,
+	PMU_RST_BY_SND_GLB_SRST		= 1,
 	PMU_RST_DISABLE			= 2,
 	WDT_GLB_SRST_CTRL_SHIFT		= 1,
 	WDT_GLB_SRST_CTRL_MASK		= BIT(1),
-	WDT_TRIGGER_SND_GLB_SRST 	= 0,
-	WDT_TRIGGER_FST_GLB_SRST 	= 1,
-	TSADC_GLB_SRST_CTRL_SHIFT 	= 0,
-	TSADC_GLB_SRST_CTRL_MASK  	= BIT(0),
-	TSADC_TRIGGER_SND_GLB_SRST 	= 0,
-	TSADC_TRIGGER_FST_GLB_SRST 	= 1,
+	WDT_TRIGGER_SND_GLB_SRST	= 0,
+	WDT_TRIGGER_FST_GLB_SRST	= 1,
+	TSADC_GLB_SRST_CTRL_SHIFT	= 0,
+	TSADC_GLB_SRST_CTRL_MASK	= BIT(0),
+	TSADC_TRIGGER_SND_GLB_SRST	= 0,
+	TSADC_TRIGGER_FST_GLB_SRST	= 1,
 
 };
 #endif

arch/arm/include/asm/arch-rockchip/f_rockusb.h

@@ -133,4 +133,3 @@ struct f_rockusb {
 /* init rockusb device, tell rockusb which device you want to read/write*/
 void rockusb_dev_init(char *dev_type, int dev_index);
 #endif /* _F_ROCKUSB_H_ */
-

arch/arm/include/asm/arch-stm32/stm32f.h

@@ -18,4 +18,3 @@
 void stm32_flash_latency_cfg(int latency);
 
 #endif /* _ASM_ARCH_STM32F_H */
-

arch/arm/include/asm/arch-stv0991/stv0991_defs.h

@@ -12,4 +12,3 @@ extern int stv0991_pinmux_config(enum periph_id);
 extern int clock_setup(enum periph_clock);
 
 #endif
-