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clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
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The H616 user manual recommends to re-parent the CPU clock during
frequency changes of the PLL, and recommends PLL_PERI0(1X), which runs
at 600 MHz. Also it asks to disable and then re-enable the PLL lock bit,
after the factor changes have been applied.

Add clock notifiers for the PLL and the CPU mux clock, using the existing
notifier callbacks, and tell them to use mux 4 (the PLL_PERI0(1X) source),
and bit 29 (the LOCK_ENABLE) bit. The existing code already follows the
correct algorithms.

Signed-off-by: Andre Przywara <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Evgeny Boger <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Andre-ARM authored and bebarino committed Jan 13, 2025
1 parent 214e7a5 commit 087b408
Showing 1 changed file with 26 additions and 2 deletions.
28 changes: 26 additions & 2 deletions drivers/clk/sunxi-ng/ccu-sun50i-h616.c
Original file line number Diff line number Diff line change
Expand Up @@ -1107,11 +1107,24 @@ static const u32 usb2_clk_regs[] = {
SUN50I_H616_USB3_CLK_REG,
};

static struct ccu_mux_nb sun50i_h616_cpu_nb = {
.common = &cpux_clk.common,
.cm = &cpux_clk.mux,
.delay_us = 1, /* manual doesn't really say */
.bypass_index = 4, /* PLL_PERI0@600MHz, as recommended by manual */
};

static struct ccu_pll_nb sun50i_h616_pll_cpu_nb = {
.common = &pll_cpux_clk.common,
.enable = BIT(29), /* LOCK_ENABLE */
.lock = BIT(28),
};

static int sun50i_h616_ccu_probe(struct platform_device *pdev)
{
void __iomem *reg;
u32 val;
int i;
int ret, i;

reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
Expand Down Expand Up @@ -1166,7 +1179,18 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev)
val |= BIT(24);
writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG);

return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc);
if (ret)
return ret;

/* Reparent CPU during CPU PLL rate changes */
ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
&sun50i_h616_cpu_nb);

/* Re-lock the CPU PLL after any rate changes */
ccu_pll_notifier_register(&sun50i_h616_pll_cpu_nb);

return 0;
}

static const struct of_device_id sun50i_h616_ccu_ids[] = {
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