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Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-sam…
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…sung' and 'clk-socfpga' into clk-next

 - Support for 5L35023 variant of Versa 3 clock generator

* clk-cleanup:
  clk: analogbits: Fix incorrect calculation of vco rate delta
  clk: Use str_enable_disable-like helpers
  clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data()
  clk: starfive: Make _clk_get become a common helper function
  clk: ep93xx: make const read-only arrays static
  clk: lmk04832: make read-only const arrays static
  clk: ti: use kcalloc() instead of kzalloc()
  dt-bindings: clock: st,stm32mp1-rcc: complete the reference path
  dt-bindings: clock: st,stm32mp1-rcc: fix reference paths
  dt-bindings: clock: ti: Convert composite.txt to json-schema
  dt-bindings: clock: ti: Convert gate.txt to json-schema
  clk: Drop obsolete devm_clk_bulk_get_all_enable() helper
  PCI: exynos: Switch to devm_clk_bulk_get_all_enabled()
  soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled()
  clk: davinci: remove platform data struct
  clk: fix an OF node reference leak in of_clk_get_parent_name()
  clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check
  clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check
  clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check

* clk-renesas: (24 commits)
  dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
  clk: renesas: r9a09g057: Add clock and reset entries for GIC
  clk: renesas: r9a09g057: Add reset entry for SYS
  clk: renesas: r8a779g0: Add VSPX clocks
  clk: renesas: r8a779g0: Add FCPVX clocks
  clk: renesas: r9a09g047: Add I2C clocks/resets
  clk: renesas: r9a09g047: Add CA55 core clocks
  clk: renesas: rzv2h: Add support for RZ/G3E SoC
  clk: renesas: rzv2h: Add MSTOP support
  dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
  dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
  dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
  clk: versaclock3: Add support for the 5L35023 variant
  dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
  clk: versaclock3: Prepare for the addition of 5L35023 device
  clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
  clk: renesas: r8a779h0: Add display clocks
  clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
  clk: renesas: rzv2h: Add selective Runtime PM support for clocks
  clk: renesas: r9a06g032: Use BIT macro consistently
  ...

* clk-mediatek:
  clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883
  clk: mediatek: mt2701-img: add missing dummy clk
  clk: mediatek: mt2701-mm: add missing dummy clk
  clk: mediatek: mt2701-bdp: add missing dummy clk
  clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe
  clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe

* clk-samsung:
  clk: samsung: Introduce Exynos990 clock controller driver
  clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}
  dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings

* clk-socfpga:
  clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
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@bebarino
bebarino committed Jan 21, 2025
5 parents d7f1285 + 83f6c3d + 830d806 + 9c2fb0c + e9f7da0 commit 70741cc
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1 change: 1 addition & 0 deletions Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@ description: |
properties:
compatible:
enum:
- renesas,5l35023
- renesas,5p35023

reg:
Expand Down
15 changes: 9 additions & 6 deletions Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -4,19 +4,22 @@
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)

maintainers:
- Lad Prabhakar <[email protected]>

description:
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
and control of clock signals for the IP modules, generation and control of resets,
and control over booting, low power consumption and power supply domains.
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
generation and control of clock signals for the IP modules, generation and
control of resets, and control over booting, low power consumption and power
supply domains.

properties:
compatible:
const: renesas,r9a09g057-cpg
enum:
- renesas,r9a09g047-cpg # RZ/G3E
- renesas,r9a09g057-cpg # RZ/V2H

reg:
maxItems: 1
Expand All @@ -37,7 +40,7 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number. The module number is calculated as the CLKON register
offset index multiplied by 16, plus the actual bit in the register
Expand Down
121 changes: 121 additions & 0 deletions Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,121 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos990 SoC clock controller

maintainers:
- Igor Belwon <[email protected]>
- Chanwoo Choi <[email protected]>
- Krzysztof Kozlowski <[email protected]>

description: |
Exynos990 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. The root clock in that root tree
is an external clock: OSCCLK (26 MHz). This external clock must be defined
as a fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
dividers; all other clocks of function blocks (other CMUs) are usually
derived from CMU_TOP.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/samsung,exynos990.h' header.
properties:
compatible:
enum:
- samsung,exynos990-cmu-hsi0
- samsung,exynos990-cmu-top

clocks:
minItems: 1
maxItems: 5

clock-names:
minItems: 1
maxItems: 5

"#clock-cells":
const: 1

reg:
maxItems: 1

required:
- compatible
- clocks
- clock-names
- "#clock-cells"
- reg

allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos990-cmu-hsi0

then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)
- description: CMU_HSI0 BUS clock (from CMU_TOP)
- description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
- description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)

clock-names:
items:
- const: oscclk
- const: bus
- const: usb31drd
- const: usbdp_debug
- const: dpgtc

- if:
properties:
compatible:
contains:
const: samsung,exynos990-cmu-top

then:
properties:
clocks:
items:
- description: External reference clock (26 MHz)

clock-names:
items:
- const: oscclk

additionalProperties: false

examples:
- |
#include <dt-bindings/clock/samsung,exynos990.h>
cmu_hsi0: clock-controller@10a00000 {
compatible = "samsung,exynos990-cmu-hsi0";
reg = <0x10a00000 0x8000>;
#clock-cells = <1>;
clocks = <&oscclk>,
<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
clock-names = "oscclk",
"bus",
"usb31drd",
"usbdp_debug",
"dpgtc";
};
...
17 changes: 17 additions & 0 deletions Documentation/devicetree/bindings/soc/renesas/renesas.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -525,6 +525,23 @@ properties:
- renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0
- const: renesas,r9a09g011

- description: RZ/G3E (R9A09G047)
items:
- enum:
- renesas,smarc2-evk # RZ SMARC Carrier-II EVK
- enum:
- renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM)
- enum:
- renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA)
- renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA)
- renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
- renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
- renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA)
- renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA)
- renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA)
- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
- const: renesas,r9a09g047

- description: RZ/V2H(P) (R9A09G057)
items:
- enum:
Expand Down
67 changes: 49 additions & 18 deletions drivers/clk/clk-versaclock3.c
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Original file line number Diff line number Diff line change
Expand Up @@ -78,9 +78,6 @@
#define VC3_PLL1_VCO_MIN 300000000UL
#define VC3_PLL1_VCO_MAX 600000000UL

#define VC3_PLL2_VCO_MIN 400000000UL
#define VC3_PLL2_VCO_MAX 1200000000UL

#define VC3_PLL3_VCO_MIN 300000000UL
#define VC3_PLL3_VCO_MAX 800000000UL

Expand Down Expand Up @@ -147,9 +144,13 @@ struct vc3_pfd_data {
u8 mdiv2_bitmsk;
};

struct vc3_vco {
unsigned long min;
unsigned long max;
};

struct vc3_pll_data {
unsigned long vco_min;
unsigned long vco_max;
struct vc3_vco vco;
u8 num;
u8 int_div_msb_offs;
u8 int_div_lsb_offs;
Expand All @@ -166,12 +167,17 @@ struct vc3_div_data {
struct vc3_hw_data {
struct clk_hw hw;
struct regmap *regmap;
const void *data;
void *data;

u32 div_int;
u32 div_frc;
};

struct vc3_hw_cfg {
struct vc3_vco pll2_vco;
u32 se2_clk_sel_msk;
};

static const struct clk_div_table div1_divs[] = {
{ .val = 0, .div = 1, }, { .val = 1, .div = 4, },
{ .val = 2, .div = 5, }, { .val = 3, .div = 6, },
Expand Down Expand Up @@ -386,10 +392,10 @@ static long vc3_pll_round_rate(struct clk_hw *hw, unsigned long rate,
const struct vc3_pll_data *pll = vc3->data;
u64 div_frc;

if (rate < pll->vco_min)
rate = pll->vco_min;
if (rate > pll->vco_max)
rate = pll->vco_max;
if (rate < pll->vco.min)
rate = pll->vco.min;
if (rate > pll->vco.max)
rate = pll->vco.max;

vc3->div_int = rate / *parent_rate;

Expand Down Expand Up @@ -680,8 +686,10 @@ static struct vc3_hw_data clk_pll[] = {
.num = VC3_PLL1,
.int_div_msb_offs = VC3_PLL1_LOOP_FILTER_N_DIV_MSB,
.int_div_lsb_offs = VC3_PLL1_VCO_N_DIVIDER,
.vco_min = VC3_PLL1_VCO_MIN,
.vco_max = VC3_PLL1_VCO_MAX
.vco = {
.min = VC3_PLL1_VCO_MIN,
.max = VC3_PLL1_VCO_MAX
}
},
.hw.init = &(struct clk_init_data) {
.name = "pll1",
Expand All @@ -698,8 +706,6 @@ static struct vc3_hw_data clk_pll[] = {
.num = VC3_PLL2,
.int_div_msb_offs = VC3_PLL2_FB_INT_DIV_MSB,
.int_div_lsb_offs = VC3_PLL2_FB_INT_DIV_LSB,
.vco_min = VC3_PLL2_VCO_MIN,
.vco_max = VC3_PLL2_VCO_MAX
},
.hw.init = &(struct clk_init_data) {
.name = "pll2",
Expand All @@ -716,8 +722,10 @@ static struct vc3_hw_data clk_pll[] = {
.num = VC3_PLL3,
.int_div_msb_offs = VC3_PLL3_LOOP_FILTER_N_DIV_MSB,
.int_div_lsb_offs = VC3_PLL3_N_DIVIDER,
.vco_min = VC3_PLL3_VCO_MIN,
.vco_max = VC3_PLL3_VCO_MAX
.vco = {
.min = VC3_PLL3_VCO_MIN,
.max = VC3_PLL3_VCO_MAX
}
},
.hw.init = &(struct clk_init_data) {
.name = "pll3",
Expand Down Expand Up @@ -901,7 +909,6 @@ static struct vc3_hw_data clk_mux[] = {
[VC3_SE2_MUX] = {
.data = &(struct vc3_clk_data) {
.offs = VC3_SE2_CTRL_REG0,
.bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
},
.hw.init = &(struct clk_init_data) {
.name = "se2_mux",
Expand Down Expand Up @@ -982,6 +989,7 @@ static int vc3_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
u8 settings[NUM_CONFIG_REGISTERS];
const struct vc3_hw_cfg *data;
struct regmap *regmap;
const char *name;
int ret, i;
Expand Down Expand Up @@ -1029,9 +1037,16 @@ static int vc3_probe(struct i2c_client *client)
clk_pfd[i].hw.init->name);
}

data = i2c_get_match_data(client);

/* Register pll's */
for (i = 0; i < ARRAY_SIZE(clk_pll); i++) {
clk_pll[i].regmap = regmap;
if (i == VC3_PLL2) {
struct vc3_pll_data *pll_data = clk_pll[i].data;

pll_data->vco = data->pll2_vco;
}
ret = devm_clk_hw_register(dev, &clk_pll[i].hw);
if (ret)
return dev_err_probe(dev, ret, "%s failed\n",
Expand Down Expand Up @@ -1059,6 +1074,11 @@ static int vc3_probe(struct i2c_client *client)
/* Register clk muxes */
for (i = 0; i < ARRAY_SIZE(clk_mux); i++) {
clk_mux[i].regmap = regmap;
if (i == VC3_SE2_MUX) {
struct vc3_clk_data *clk_data = clk_mux[i].data;

clk_data->bitmsk = data->se2_clk_sel_msk;
}
ret = devm_clk_hw_register(dev, &clk_mux[i].hw);
if (ret)
return dev_err_probe(dev, ret, "%s failed\n",
Expand Down Expand Up @@ -1108,8 +1128,19 @@ static int vc3_probe(struct i2c_client *client)
return ret;
}

static const struct vc3_hw_cfg vc3_5p = {
.pll2_vco = { .min = 400000000UL, .max = 1200000000UL },
.se2_clk_sel_msk = BIT(6),
};

static const struct vc3_hw_cfg vc3_5l = {
.pll2_vco = { .min = 30000000UL, .max = 130000000UL },
.se2_clk_sel_msk = BIT(0),
};

static const struct of_device_id dev_ids[] = {
{ .compatible = "renesas,5p35023" },
{ .compatible = "renesas,5p35023", .data = &vc3_5p },
{ .compatible = "renesas,5l35023", .data = &vc3_5l },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dev_ids);
Expand Down
10 changes: 10 additions & 0 deletions drivers/clk/mediatek/clk-mt2701-aud.c
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Original file line number Diff line number Diff line change
Expand Up @@ -55,10 +55,16 @@ static const struct mtk_gate audio_clks[] = {
GATE_DUMMY(CLK_DUMMY, "aud_dummy"),
/* AUDIO0 */
GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
GATE_DUMMY(CLK_AUD_LRCK_DETECT, "audio_lrck_detect_dummy"),
GATE_DUMMY(CLK_AUD_I2S, "audio_i2c_dummy"),
GATE_DUMMY(CLK_AUD_APLL_TUNER, "audio_apll_tuner_dummy"),
GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
GATE_DUMMY(CLK_AUD_TML, "audio_tml_dummy"),
GATE_DUMMY(CLK_AUD_AHB_IDLE_EXT, "audio_ahb_idle_ext_dummy"),
GATE_DUMMY(CLK_AUD_AHB_IDLE_INT, "audio_ahb_idle_int_dummy"),
/* AUDIO1 */
GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
Expand All @@ -76,10 +82,12 @@ static const struct mtk_gate audio_clks[] = {
GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
GATE_DUMMY(CLK_AUD_HDMIRX, "audio_hdmirx_dummy"),
GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
GATE_DUMMY(CLK_AUD_AFE_PCMIF, "audio_afe_pcmif_dummy"),
GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
/* AUDIO2 */
GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
Expand All @@ -100,6 +108,8 @@ static const struct mtk_gate audio_clks[] = {
GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
/* AUDIO3 */
GATE_DUMMY(CLK_AUD_DMIC1, "audio_dmic1_dummy"),
GATE_DUMMY(CLK_AUD_DMIC2, "audio_dmic2_dummy"),
GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
Expand Down
1 change: 1 addition & 0 deletions drivers/clk/mediatek/clk-mt2701-bdp.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@ static const struct mtk_gate_regs bdp1_cg_regs = {
GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)

static const struct mtk_gate bdp_clks[] = {
GATE_DUMMY(CLK_DUMMY, "bdp_dummy"),
GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
Expand Down
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