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SKARAB 40gbe extraction commit #5
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So it turns out that each core needs its own MEZ3_REFCLK, dhop!
No wonder it couldnt place and route the clocks from another bank
to my 2nd core.
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@wnew
wnew committed Jul 17, 2019
1 parent 0a53d0c commit 80cfe04
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Showing 3 changed files with 47 additions and 27 deletions.
4 changes: 2 additions & 2 deletions jasper_library/hdl_sources/forty_gbe/forty_gbe.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -48,8 +48,8 @@ entity forty_gbe is
sys_clk : in std_logic;
sys_rst : in std_logic;

MEZ3_REFCLK_0_P : in std_logic;
MEZ3_REFCLK_0_N : in std_logic;
MEZ3_REFCLK_P : in std_logic;
MEZ3_REFCLK_N : in std_logic;

qsfp_gtrefclk : out std_logic;
qsfp_soft_reset : in std_logic;
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48 changes: 41 additions & 7 deletions jasper_library/yellow_blocks/forty_gbe.py
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Original file line number Diff line number Diff line change
Expand Up @@ -52,8 +52,8 @@ def modify_top(self,top):
self.mez3_phy == "PHY11"
self.clock_region = "CLOCKREGION_X1Y7:CLOCKREGION_X1Y7"

inst.add_port('MEZ3_REFCLK_0_P', 'MEZ3_REFCLK_0_P', parent_port=True, dir='in')
inst.add_port('MEZ3_REFCLK_0_N', 'MEZ3_REFCLK_0_N', parent_port=True, dir='in')
inst.add_port('MEZ3_REFCLK_P', 'MEZ3_REFCLK_%s_P'%self.port, parent_port=True, dir='in')
inst.add_port('MEZ3_REFCLK_N', 'MEZ3_REFCLK_%s_N'%self.port, parent_port=True, dir='in')
inst.add_port('MEZ3_PHY_LANE_RX_P', 'MEZ3_'+self.mez3_phy+'_LANE_RX_P', parent_port=True, dir='in', width=4)
inst.add_port('MEZ3_PHY_LANE_RX_N', 'MEZ3_'+self.mez3_phy+'_LANE_RX_N', parent_port=True, dir='in', width=4)
inst.add_port('MEZ3_PHY_LANE_TX_P', 'MEZ3_'+self.mez3_phy+'_LANE_TX_P', parent_port=True, dir='out', width=4)
Expand Down Expand Up @@ -166,15 +166,49 @@ def gen_constraints(self):
cons.append(PortConstraint('MEZ3_'+self.mez3_phy+'_LANE_TX_N', 'MEZ3_'+self.mez3_phy+'_LANE_TX_N', port_index=range(4), iogroup_index=range(4)))
cons.append(PortConstraint('MEZ3_'+self.mez3_phy+'_LANE_RX_P', 'MEZ3_'+self.mez3_phy+'_LANE_RX_P', port_index=range(4), iogroup_index=range(4)))
cons.append(PortConstraint('MEZ3_'+self.mez3_phy+'_LANE_RX_N', 'MEZ3_'+self.mez3_phy+'_LANE_RX_N', port_index=range(4), iogroup_index=range(4)))
cons.append(PortConstraint('MEZ3_REFCLK_0_P','MEZ3_REFCLK_0_P'))
cons.append(PortConstraint('MEZ3_REFCLK_0_N','MEZ3_REFCLK_0_N'))
cons.append(ClockConstraint('MEZ3_REFCLK_0_P','MEZ3_REFCLK_0_P', period=6.4, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=3.2))
cons.append(PortConstraint('MEZ3_REFCLK_P','MEZ3_REFCLK_%s_P'%self.port))
cons.append(PortConstraint('MEZ3_REFCLK_N','MEZ3_REFCLK_%s_N'%self.port))
cons.append(ClockConstraint('MEZ3_REFCLK_%s_P'%self.port,'MEZ3_REFCLK_%s_P'%self.port, period=6.4, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=3.2))

cons.append(RawConstraint('create_pblock MEZ3_'+self.mez3_phy+'_QSFP'))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_'+str(self.port)+'/PHY_inst/RX_CLK_RCC]]'))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_'+str(self.port)+'/PHY_inst/TX_CLK_RCC]]'))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_0/PHY_inst/RX_CLK_RCC]]'))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_0/PHY_inst/TX_CLK_RCC]]'))
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] -add {'+self.clock_region+'}'))

#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_clkout0', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(ClockGroupConstraint('virtual_clock', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'FPGA_EMCCLK2', 'asynchronous'))
cons.append(ClockGroupConstraint('FPGA_EMCCLK2', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'virtual_clock', 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_I', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'VIRTUAL_I','asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_%s_P'%self.port, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_%s_P'%self.port, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_%s_P'%self.port, multicycledelay=4))
cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_%s_P'%self.port, multicycledelay=4))
















return cons


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22 changes: 4 additions & 18 deletions jasper_library/yellow_blocks/skarab.py
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Original file line number Diff line number Diff line change
Expand Up @@ -386,25 +386,19 @@ def gen_constraints(self):
#cons.append(ClockGroupConstraint('-include_generated_clocks FPGA_REFCLK_BUF1_P', 'get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
#cons.append(ClockGroupConstraint('FPGA_EMCCLK2', '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_0_0_P', '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
#cons.append(ClockGroupConstraint('virtual_clock', '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
#cons.append(ClockGroupConstraint('VIRTUAL_clkout0', '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'FPGA_EMCCLK2', 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_0_P', 'asynchronous'))
cons.append(ClockGroupConstraint('%s/wishbone_flash_sdram_interface_0/icape_controller_0/CLK' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '%s/wishbone_flash_sdram_interface_0/icape_controller_0/CLK' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('FPGA_EMCCLK2', '-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_0_P', '-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_clkout0', 'FPGA_EMCCLK2', 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_clkout0_1', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_clkout0_1', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'VIRTUAL_clkout0_1', 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_clkout0', 'MEZ3_REFCLK_0_P', 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_0_P', 'FPGA_EMCCLK2', 'asynchronous'))
cons.append(ClockGroupConstraint('FPGA_EMCCLK2', 'MEZ3_REFCLK_0_P', 'asynchronous'))

cons.append(ClockGroupConstraint('VIRTUAL_clkout0', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('virtual_clock', 'FPGA_EMCCLK2', 'asynchronous'))
cons.append(ClockGroupConstraint('virtual_clock', 'MEZ3_REFCLK_0_P', 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'VIRTUAL_clkout0_1', 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
Expand All @@ -423,7 +417,7 @@ def gen_constraints(self):

cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'VIRTUAL_clkout0_1', 'asynchronous'))

cons.append(ClockGroupConstraint('MEZ3_REFCLK_0_P', 'virtual_clock', 'asynchronous'))

cons.append(ClockGroupConstraint('VIRTUAL_clkout0', 'virtual_clock', 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_I', 'virtual_clock', 'asynchronous'))
cons.append(ClockGroupConstraint('virtual_clock', 'VIRTUAL_I', 'asynchronous'))
Expand All @@ -435,22 +429,17 @@ def gen_constraints(self):
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'VIRTUAL_I', 'asynchronous'))
#cons.append(ClockGroupConstraint('-include_generated_clocks FPGA_REFCLK_BUF1_P', 'VIRTUAL_I', 'asynchronous'))
#cons.append(ClockGroupConstraint('VIRTUAL_I', '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_I', 'MEZ3_REFCLK_0_P', 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_0_P', 'VIRTUAL_I','asynchronous'))


cons.append(ClockGroupConstraint('FPGA_EMCCLK2', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'FPGA_EMCCLK2', 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_0_P', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'MEZ3_REFCLK_0_P', 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_clkout0', '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'VIRTUAL_clkout0', 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' % self.fullname, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, '-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' % self.fullname, 'asynchronous'))

cons.append(ClockGroupConstraint('FPGA_EMCCLK2', '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'FPGA_EMCCLK2', 'asynchronous'))
cons.append(ClockGroupConstraint('MEZ3_REFCLK_0_P', '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_0_P', 'asynchronous'))
cons.append(ClockGroupConstraint('VIRTUAL_clkout0', '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'VIRTUAL_clkout0', 'asynchronous'))

Expand All @@ -475,8 +464,6 @@ def gen_constraints(self):
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='FPGA_EMCCLK2', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='FPGA_EMCCLK2', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_0_P', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_0_P', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='VIRTUAL_clkout0', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='VIRTUAL_clkout0', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N'))
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='I2C_SCL_FPGA'))
Expand Down Expand Up @@ -719,8 +706,7 @@ def gen_constraints(self):
cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, multicycledelay=3))
cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks VIRTUAL_clkout0', multicycledelay=4))
cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks VIRTUAL_clkout0', multicycledelay=3))
cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_0_P', multicycledelay=4))
cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_0_P', multicycledelay=4))

cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks FPGA_EMCCLK2', multicycledelay=4))
cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks FPGA_EMCCLK2', multicycledelay=3))
cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, destpath='get_ports MEZZANINE_0_ENABLE_N', multicycledelay=4))
Expand Down

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