Simplify Minimal target

castor-software · Nov 1, 2020 · ee8157a · ee8157a
1 parent b8654db
commit ee8157a
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Showing 3 changed files with 7 additions and 10 deletions.
diff --git a/src/unison/src/Unison/Target/Minimal.hs b/src/unison/src/Unison/Target/Minimal.hs
@@ -22,7 +22,6 @@ import qualified Unison.Target.API as API
 import Unison.Target.RegisterArray
 
 import Unison.Target.Minimal.MinimalRegisterDecl
-import Unison.Target.Minimal.MinimalResourceDecl
 import Unison.Target.Minimal.SpecsGen.MinimalInstructionDecl
 import Unison.Target.Minimal.SpecsGen.MinimalRegisterClassDecl
 import qualified Unison.Target.Minimal.SpecsGen as SpecsGen
@@ -196,6 +195,13 @@ packedPairs _ _ = []
 -- | Gives pairs of operands whose registers are related extensionally
 relatedPairs _ = []
 
+data MinimalResource =
+  -- Size of each instruction
+  BundleWidth |
+  -- Simple resource to enforce single-issue
+  Issue
+  deriving (Eq, Ord, Show, Read)
+
 -- | Declares target architecture resources. An issue width of w can be
 -- specified with the option --targetoption=issue-width:w.
 resources to =

diff --git a/src/unison/src/Unison/Target/Minimal/MinimalResourceDecl.hs b/src/unison/src/Unison/Target/Minimal/MinimalResourceDecl.hs
diff --git a/src/unison/unison.cabal b/src/unison/unison.cabal
@@ -262,7 +262,6 @@ Library
                   Unison.Target.Mips.SpecsGen.Parent
 
                   Unison.Target.Minimal.MinimalRegisterDecl
-                  Unison.Target.Minimal.MinimalResourceDecl
                   Unison.Target.Minimal.SpecsGen
                   Unison.Target.Minimal.SpecsGen.MinimalInstructionDecl
                   Unison.Target.Minimal.SpecsGen.MinimalItineraryDecl