Add CBAR register and fix TE bit #6
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rustc already has target cfg's for these
Add an SVC example too.
If we boot at EL2, we manage to switch to EL1, however performing a 'SVC' instruction puts us in a mode where our stack pointer is NULL, crashing the CPU. The default exception handler also does semihosting now.
* Tested on armv7r-none-eabi, armv7r-none-eabihf and an armv8r-none-eabihf machine that boots into EL2 * Used macros to de-duplicate the exception entry and exit code. * Set up different stacks for the various different modes.
Let the compiler pick A32 or T32.
It would be bad for an operation that should be in a critical-section to move to the other side.
This helped me find a bug in my IRQ handler, where Armv7-R and Armv8-R AArch32 both state that an IRQ exception is given an address in LR that is four bytes larger than the actual return address. Because of pipeline issues back in the mid-1980s or something.
We need the const-asm support that was added.
We can get LLVM to store LR, if and only if it needs to, by marking it as clobbered. The SPRS is handled by the SVC trampoline, even if we SVC inside an SVC.
Helps the debugger understand where one function ends and another begins.
Both my test chip and QEMU return zero from CBAR though, which is unhelpful.
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As we can't compile any Thumb code for Armv7-R or Armv8-R in Rust (as it stands), we're always going to have Arm Exceptions not Thumb Exceptions.
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Adds access to the CBAR register, and ensures the TE bit is not set so we don't attempt to execute Exceptions in Thumb mode (the Rust compiler can only generate A32 instructions for this target).
Requires #5