Chisel 5

freechipsproject · Nov 7, 2024 · cc54b8d · cc54b8d
1 parent 90358a3
commit cc54b8d
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Showing 8 changed files with 11 additions and 19 deletions.
diff --git a/build.sbt b/build.sbt
@@ -1,8 +1,7 @@
 // See README.md for license details.
 
 ThisBuild / scalaVersion     := "2.13.14"
-// ThisBuild / crossScalaVersions := Seq("2.12.17", "2.13.10")
-ThisBuild / version          := "0.6.1"
+ThisBuild / version          := "5.0.0"
 
 
 lazy val publishSettings = Seq (
@@ -29,20 +28,22 @@ lazy val publishSettings = Seq (
   ),
 )
 
+val chiselVersion = "5.3.0"
+
 lazy val root = (project in file("."))
   .settings(
     name := "ip-contributions",
     resolvers += Resolver.sonatypeRepo("snapshots"),
     libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chisel3" % "3.6.1",
-      "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % "test",
+      "org.chipsalliance" %% "chisel" % chiselVersion,
+      "edu.berkeley.cs" %% "chiseltest" % "5.0.2" % "test",
     ),
     scalacOptions ++= Seq(
       "-language:reflectiveCalls",
       "-deprecation",
       "-feature",
       "-Xcheckinit",
     ),
-    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.1" cross CrossVersion.full),
+    addCompilerPlugin("org.chipsalliance" %% "chisel-plugin" % chiselVersion cross CrossVersion.full),
   )
   .settings(publishSettings: _*)
diff --git a/src/main/scala/chisel/lib/bitonicsorter/BitonicSorter.scala b/src/main/scala/chisel/lib/bitonicsorter/BitonicSorter.scala
@@ -3,7 +3,6 @@
 package chisel.lib.bitonicsorter
 
 import chisel3._
-import chisel3.stage.ChiselStage
 import chisel3.util._
 
 /**

diff --git a/src/main/scala/chisel/lib/spi/Spi.scala b/src/main/scala/chisel/lib/spi/Spi.scala
@@ -8,8 +8,6 @@
 package chisel.lib.spi
 
 import chisel3._
-import chisel3.experimental.Analog
-import chisel3.stage.ChiselStage
 import chisel3.util._
 
 class Master(frequency: Int, clkfreq: Int, bsize: Int) extends Module {

diff --git a/src/main/scala/chisel/lib/uart/Uart.scala b/src/main/scala/chisel/lib/uart/Uart.scala
@@ -9,7 +9,6 @@
 package chisel.lib.uart
 
 import chisel3._
-import chisel3.stage.ChiselStage
 import chisel3.util._
 
 class UartIO extends DecoupledIO(UInt(8.W))
@@ -207,5 +206,5 @@ class UartMain(frequency: Int, baudRate: Int) extends Module {
 }
 
 object UartMain extends App {
-  (new ChiselStage).emitSystemVerilog(new UartMain(50000000, 115200), Array("--target-dir", "generated"))
+  emitVerilog(new UartMain(50000000, 115200), Array("--target-dir", "generated"))
 }
diff --git a/src/test/scala/chisel/lib/ecc/EccTester.scala b/src/test/scala/chisel/lib/ecc/EccTester.scala
@@ -3,7 +3,6 @@
 package chisel.lib.ecc
 
 import chisel3._
-import chisel3.stage.ChiselStage
 import chiseltest._
 import org.scalatest.freespec.AnyFreeSpec
 
@@ -152,5 +151,5 @@ class EccTester extends AnyFreeSpec with ChiselScalatestTester {
 }
 
 object EccGenerator extends App {
-  (new ChiselStage).emitSystemVerilog(new EccCheck(UInt(8.W)), Array("--target-dir", "generated"))
+  emitVerilog(new EccCheck(UInt(8.W)), Array("--target-dir", "generated"))
 }
diff --git a/src/test/scala/chisel/lib/fifo/FifoFormalTest.scala b/src/test/scala/chisel/lib/fifo/FifoFormalTest.scala
@@ -6,11 +6,10 @@ import chisel3._
 import chisel3.util._
 import chiseltest._
 import chiseltest.formal._
-import firrtl.AnnotationSeq
 import org.scalatest.flatspec.AnyFlatSpec
 
 class FifoFormalTest extends AnyFlatSpec with ChiselScalatestTester with Formal {
-  private val defaultOptions: AnnotationSeq = Seq(BoundedCheck(10))
+  private val defaultOptions = Seq(BoundedCheck(10))
 
   "BubbleFifo" should "pass" in {
     verify(new FifoTestWrapper(new BubbleFifo(UInt(16.W), 4)), defaultOptions)

diff --git a/src/test/scala/chisel/lib/fifo/FifoSpec.scala b/src/test/scala/chisel/lib/fifo/FifoSpec.scala
@@ -5,7 +5,6 @@ package chisel.lib.fifo
 
 import chisel3._
 import chiseltest._
-import firrtl.AnnotationSeq
 import org.scalatest.flatspec.AnyFlatSpec
 
 /**
@@ -177,7 +176,7 @@ object testFifo {
 }
 
 class FifoSpec extends AnyFlatSpec with ChiselScalatestTester {
-  private val defaultOptions: AnnotationSeq = Seq(WriteVcdAnnotation)
+  private val defaultOptions = Seq(WriteVcdAnnotation)
 
   "BubbleFifo" should "pass" in {
     test(new BubbleFifo(UInt(16.W), 4)).withAnnotations(defaultOptions)(testFifo(_, 2))

diff --git a/src/test/scala/chisel/lib/fifo/SimpleFifoFormal.scala b/src/test/scala/chisel/lib/fifo/SimpleFifoFormal.scala
@@ -3,14 +3,12 @@
 package chisel.lib.fifo
 
 import chisel3._
-import chisel3.util._
 import chiseltest._
 import chiseltest.formal._
-import firrtl.AnnotationSeq
 import org.scalatest.flatspec.AnyFlatSpec
 
 class SimpleFifoFormal extends AnyFlatSpec with ChiselScalatestTester with Formal {
-  private val defaultOptions: AnnotationSeq = Seq(BoundedCheck(10), WriteVcdAnnotation)
+  private val defaultOptions = Seq(BoundedCheck(10), WriteVcdAnnotation)
 
   "RegFifo" should "pass formal verification" in {
     verify(new RegFifo(UInt(16.W), 4), defaultOptions)