Bootstrap project

.github/workflows/build_project.yml

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+name: Build Project
+
+on:
+  push:
+    branches: [ "master" ]
+  pull_request:
+    branches: [ "master" ]
+
+jobs:
+  build:
+
+    runs-on: ubuntu-latest
+
+    steps:
+    - name: Update apt-get
+      run: sudo apt-get update
+    - name: Install prerequisites
+      run: sudo apt-get install -y verilator
+    - uses: actions/checkout@v4
+    - name: Build Release
+      run: make -j12
+    - name: Simulate
+      run: ./obj_dir/Vtop
+    - name: Upload artifacts
+      uses: actions/upload-artifact@v4
+      with:
+        name: Simulation Artifacts
+        path: |
+            toptrace.vcd

.gitignore

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+obj_dir/*
+
+*.vcd

.vscode/launch.json

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+{
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "name": "Python Debugger: Current File",
+            "type": "debugpy",
+            "request": "launch",
+            "program": "${workspaceFolder}/assembler/main.py",
+            "args": [
+                "${workspaceFolder}/assembler/UART_hello.asm"
+            ],
+            "console": "integratedTerminal"
+        }
+    ]
+}

LICENSE

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+MIT License
+
+Copyright (c) 2024 Fredrik Sævland
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

Makefile

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+
+.PHONY: all
+all: top
+
+
+VERILATOR=verilator
+VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e "s/^.*=\s*//"')
+VINC := $(VERILATOR_ROOT)/include
+TARGET_VERILOG_FOLDER=./verilog
+TARGET_VERILATOR_FOLDER=./verilator_testbench
+
+# Ideally, we'd want -GWIDTH=12
+# This requires a newer version of Verilator than I have with my distro
+# Hence we have the `ifdef inside gpu.v
+top: $(TARGET_VERILATOR_FOLDER)/top.cpp $(TARGET_VERILOG_FOLDER)/top.sv
+		$(VERILATOR) -cc --exe -trace --build -j 0 -Wall -I"$(TARGET_VERILOG_FOLDER)" --top-module top $(TARGET_VERILATOR_FOLDER)/top.cpp $(TARGET_VERILOG_FOLDER)/top.sv
+
+toptrace.vcd: top obj_dir/Vtop
+	obj_dir/Vtop
+
+view: toptrace.vcd
+	gtkwave toptrace.vcd
+
+.PHONY: clean
+clean:
+	rm -rf obj_dir/ top toptrace.vcd

Project-Fetchie.code-workspace

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+{
+	"folders": [
+		{
+			"path": "."
+		}
+	],
+	"settings": {}
+}

default_view.gtkw

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+[*]
+[*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI
+[*] Fri Feb 23 23:32:29 2024
+[*]
+[dumpfile] "/home/gavekort/TinyMCU/toptrace.vcd"
+[dumpfile_mtime] "Fri Feb 23 23:14:43 2024"
+[dumpfile_size] 295923068
+[savefile] "/home/gavekort/TinyMCU/default_view.gtkw"
+[timestart] 7894437
+[size] 2560 1366
+[pos] -1 -1
+*-10.876068 7906675 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] TOP.
+[treeopen] TOP.top.
+[treeopen] TOP.top.cpu_inst.
+[treeopen] TOP.top.cpu_inst.controller.
+[sst_width] 243
+[signals_width] 236
+[sst_expanded] 1
+[sst_vpaned_height] 919
+@28
+[color] 1
+TOP.top.cpu_inst.controller.clk
+@c00022
+[color] 1
+TOP.top.cpu_inst.controller.opcode[7:0]
+@28
+[color] 1
+(0)TOP.top.cpu_inst.controller.opcode[7:0]
+[color] 1
+(1)TOP.top.cpu_inst.controller.opcode[7:0]
+[color] 1
+(2)TOP.top.cpu_inst.controller.opcode[7:0]
+[color] 1
+(3)TOP.top.cpu_inst.controller.opcode[7:0]
+[color] 1
+(4)TOP.top.cpu_inst.controller.opcode[7:0]
+[color] 1
+(5)TOP.top.cpu_inst.controller.opcode[7:0]
+[color] 1
+(6)TOP.top.cpu_inst.controller.opcode[7:0]
+[color] 1
+(7)TOP.top.cpu_inst.controller.opcode[7:0]
+@1401200
+-group_end
+@22
+[color] 1
+TOP.top.cpu_inst.controller.stage[3:0]
+@28
+TOP.top.cpu_inst.controller.cnt_en
+@22
+TOP.top.cpu_inst.addr[15:0]
+@28
+[color] 7
+TOP.top.cpu_inst.areg_out
+[color] 7
+TOP.top.cpu_inst.breg_out
+[color] 7
+TOP.top.cpu_inst.hreg_out
+[color] 7
+TOP.top.cpu_inst.lreg_out
+[color] 7
+TOP.top.cpu_inst.controller.alu_out
+[color] 7
+TOP.top.cpu_inst.cnt_l_out
+[color] 7
+TOP.top.cpu_inst.cnt_h_out
+[color] 7
+TOP.top.cpu_inst.controller.ram_read_pc
+[color] 7
+TOP.top.cpu_inst.controller.ram_read_mreg
+[color] 7
+TOP.top.cpu_inst.controller.cnt_wr
+[color] 3
+TOP.top.cpu_inst.controller.mreg_h_load
+[color] 3
+TOP.top.cpu_inst.controller.mreg_l_load
+[color] 3
+TOP.top.cpu_inst.controller.areg_load
+[color] 3
+TOP.top.cpu_inst.controller.breg_load
+[color] 3
+TOP.top.cpu_inst.ireg_load
+@22
+TOP.top.cpu_inst.data[7:0]
+TOP.top.cpu_inst.addr[15:0]
+TOP.top.cpu_inst.alu_inst.alu_mode[7:0]
+@100000028
+[color] 2
+TOP.top.cpu_inst.controller.alu_zero
+@28
+[color] 2
+TOP.top.cpu_inst.alu_carry
+@22
+[color] 2
+TOP.top.cpu_inst.alu_data_out[7:0]
+[color] 2
+TOP.top.cpu_inst.areg_data_out[7:0]
+[color] 2
+TOP.top.cpu_inst.breg_data_out[7:0]
+@28
+TOP.top.cpu_inst.cnt_wr
+@22
+TOP.top.uart_inst.DO[7:0]
+@28
+TOP.top.uart_inst.tx
+@820
+TOP.top.uart_inst.byte_out[9:0]
+@22
+TOP.top.cpu_inst.hreg.data_out[7:0]
+@23
+TOP.top.cpu_inst.lreg.data_out[7:0]
+[pattern_trace] 1
+[pattern_trace] 0

verilator_testbench/top.cpp

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+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: 	blinky.cpp
+//
+// Project:	Verilog Tutorial Example file
+//
+// Purpose:	Drives the LED blinking design Verilator simulation
+//
+// Creator:	Dan Gisselquist, Ph.D.
+//		Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Written and distributed by Gisselquist Technology, LLC
+//
+// This program is hereby granted to the public domain.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+#include <stdio.h>
+#include <stdlib.h>
+#include <iostream>
+#include "Vtop.h"
+#include "verilated.h"
+#include "verilated_vcd_c.h"
+
+enum opcodes {
+    NOP = 0x00,
+    HALT = 0x01,
+    LDAim = 0x02,
+    LDA = 0x03,
+    STA = 0x04
+};
+
+uint8_t program[] = {
+    NOP, LDAim, 0xde, STA, 0xfe, 0xed,
+    0x01
+};
+
+uint16_t prog_idx = 0;
+
+enum class tb_states {
+    START,
+    PROG,
+    RUN,
+    HALT
+};
+
+tb_states state = tb_states::START;
+
+bool tick(int tickcount, Vtop *top, VerilatedVcdC* tfp) {
+    top->clk_in = tickcount % 2;
+    top->eval(); //Run module
+
+    // switch(state){
+    //     case tb_states::START:
+    //         top->reset_in = 1;
+    //         if(tickcount > 10){
+    //             printf("Program load\n");
+    //             state = tb_states::PROG;
+    //         }
+    //         break;
+    //     case tb_states::PROG:
+    //         // top->reset_in = 0;
+    //         // top->prog_in = 1;
+
+    //         // top->data_in = program[prog_idx++];
+    //         // top->addr_in = prog_idx;
+
+    //         if(prog_idx >= sizeof(program)){
+    //             printf("Program loaded\n");
+    //             top->prog_in = 0;
+    //             state = tb_states::RUN;
+    //         }
+    //         break;
+    //     case tb_states::RUN:
+
+    //         break;
+    //     case tb_states::HALT:
+    //         return true;
+    // }
+    // if (top->irq)
+    // {
+    //     std::cout << "Got IRQ, acking" << std::endl;
+    //     top->irq_ack = 1;
+    // }else{
+    //     top->irq_ack = 0;
+    // }
+    if(tickcount > 10000000){
+        printf("Exceeded simulation limit, halting\n");
+        return true;
+    }
+    if (tfp){ //If dumpfile
+        tfp->dump(tickcount * 25);
+    }
+    return false;
+}
+
+int main(int argc, char** argv) {
+    int counter = 0;
+    bool running = true;
+    VerilatedContext* contextp = new VerilatedContext;
+    contextp->commandArgs(argc, argv);
+    Vtop* top = new Vtop{contextp};
+
+	// Generate a trace
+	Verilated::traceEverOn(true);
+	VerilatedVcdC* tfp = new VerilatedVcdC;
+	top->trace(tfp, 00);
+	tfp->open("toptrace.vcd");
+    top->reset_in = 1;
+
+    while (!contextp->gotFinish() && running) {
+        if(tick(++counter, top, tfp)){
+            running = false;
+        }
+    }
+    tfp->flush();
+    delete top;
+    delete contextp;
+    delete tfp;
+    return 0;
+}

verilog/cache.sv

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+/* verilator lint_off UNUSED */
+/* verilator lint_off UNDRIVEN*/
+/* verilator lint_off DECLFILENAME*/
+/* verilator lint_off PINMISSING */
+
+module cache(
+    input clk,
+    input [31:0] addr_in,
+    input [31:0] data_in
+);
+
+    fifo #(.SIZE(1024)) fifo_inst(.clk(clk), .reset(0), .wr_en(1), .rd_en(0), .data_in(data_in), .data_out(0), .empty(0), .full(0));
+
+endmodule

verilog/counter.sv

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+module counter(input clk, input load, input enable, input cnt_up, input [31:0] data_in, output reg [31:0] data_out);
+
+    always @(posedge clk)
+    begin
+        if (load) begin
+            data_out <= data_in;
+        end
+        else if (enable) begin
+            if (cnt_up)
+                data_out <= data_out + 32'h00000001;
+            else
+                data_out <= data_out - 32'h00000001;
+        end
+    end
+endmodule