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modules/zstd: Add LiteralsDecoder implementation
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Signed-off-by: Maciej Torhan <[email protected]>
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@m-torhan @mtdudek
m-torhan authored and mtdudek committed Jul 25, 2024
1 parent d880116 commit 7143a28
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Showing 6 changed files with 841 additions and 36 deletions.
98 changes: 98 additions & 0 deletions xls/modules/zstd/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -1408,3 +1408,101 @@ place_and_route(
synthesized_rtl = ":literals_buffer_synth_asap7",
target_die_utilization_percentage = "10",
)

xls_dslx_library(
name = "literals_decoder_dslx",
srcs = [
"literals_decoder.x",
],
deps = [
"//xls/examples:ram_dslx",
":common_dslx",
":literals_buffer_dslx",
":literals_dispatcher_dslx",
":parallel_rams_dslx",
":ram_printer_dslx",
":raw_literals_dec_dslx",
":rle_literals_dec_dslx",
],
)

xls_dslx_test(
name = "literals_decoder_dslx_test",
library = ":literals_decoder_dslx",
)

xls_dslx_verilog(
name = "literals_decoder_verilog",
codegen_args = {
"module_name": "LiteralsDecoder",
"delay_model": "asap7",
"ram_configurations": ",".join([
"{ram_name}:1R1W:{rd_req}:{rd_resp}:{wr_req}:{wr_resp}:{latency}".format(
latency = 5,
ram_name = "ram{}".format(num),
rd_req = "literals_decoder__rd_req_m{}_s".format(num),
rd_resp = "literals_decoder__rd_resp_m{}_r".format(num),
wr_req = "literals_decoder__wr_req_m{}_s".format(num),
wr_resp = "literals_decoder__wr_resp_m{}_r".format(num),
)
for num in range(7)
]),
"pipeline_stages": "8",
"reset": "rst",
"worst_case_throughput": "1",
"use_system_verilog": "false",
},
dslx_top = "LiteralsDecoderInst",
library = ":literals_decoder_dslx",
opt_ir_args = {
"inline_procs": "true",
"top": "__xls_modules_zstd_literals_buffer__LiteralsDecoderInst__LiteralsDecoder__LiteralsBuffer__LiteralsBufferReader_0__64_0_0_0_13_8192_65536_next",
},
verilog_file = "literals_decoder.v",
)

xls_benchmark_ir(
name = "literals_decoder_opt_ir_benchmark",
src = ":literals_decoder_verilog.opt.ir",
benchmark_ir_args = {
"pipeline_stages": "10",
"delay_model": "asap7",
},
)

xls_benchmark_verilog(
name = "literals_decoder_verilog_benchmark",
verilog_target = "literals_decoder_verilog",
)

verilog_library(
name = "literals_decoder_verilog_lib",
srcs = [
":literals_decoder.v",
],
)

synthesize_rtl(
name = "literals_decoder_synth_asap7",
standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt",
top_module = "LiteralsDecoder",
deps = [
":literals_decoder_verilog_lib",
],
)

benchmark_synth(
name = "literals_decoder_benchmark_synth",
synth_target = ":literals_decoder_synth_asap7",
)

place_and_route(
name = "literals_decoder_place_and_route",
clock_period = "750",
core_padding_microns = 2,
min_pin_distance = "0.5",
placement_density = "0.30",
stop_after_step = "global_routing",
synthesized_rtl = ":literals_decoder_synth_asap7",
target_die_utilization_percentage = "10",
)
43 changes: 17 additions & 26 deletions xls/modules/zstd/literals_buffer.x
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Original file line number Diff line number Diff line change
Expand Up @@ -39,13 +39,14 @@ type RamNumber = parallel_rams::RamNumber;
type RamReadStart = parallel_rams::RamReadStart;
type RamRdRespHandlerData = parallel_rams::RamRdRespHandlerData;
type RamWrRespHandlerData = parallel_rams::RamWrRespHandlerData;
type RamWrRespHandlerResp = parallel_rams::RamWrRespHandlerResp;

// Constants calculated from RAM parameters
const RAM_NUM = parallel_rams::RAM_NUM;
pub const RAM_NUM = parallel_rams::RAM_NUM;
const RAM_NUM_WIDTH = parallel_rams::RAM_NUM_WIDTH;
const RAM_DATA_WIDTH = common::SYMBOL_WIDTH + u32:1; // the +1 is used to store "last" flag
const RAM_WORD_PARTITION_SIZE = RAM_DATA_WIDTH;
const RAM_NUM_PARTITIONS = ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH);
pub const RAM_DATA_WIDTH = common::SYMBOL_WIDTH + u32:1; // the +1 is used to store "last" flag
pub const RAM_WORD_PARTITION_SIZE = RAM_DATA_WIDTH;
pub const RAM_NUM_PARTITIONS = ram::num_partitions(RAM_WORD_PARTITION_SIZE, RAM_DATA_WIDTH);

// Literals data with last flag
type LiteralsWithLast = uN[RAM_DATA_WIDTH * RAM_NUM];
Expand Down Expand Up @@ -80,7 +81,6 @@ struct LiteralsBufferWriterState<RAM_ADDR_WIDTH: u32> {
// History Buffer handling
hyp_ptr: HistoryBufferPtr<RAM_ADDR_WIDTH>,
hb_len: uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH],
prev_wr_comp: HistoryBufferPtr<RAM_ADDR_WIDTH>,
literals_in_ram: uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH],
}

Expand Down Expand Up @@ -339,17 +339,17 @@ proc LiteralsBufferMux {
let (literals_data, state) = if (sel_raw_literals) {
(
state.raw_literals_data,
LiteralsBufferMuxState { raw_literals_valid: false, ..state }
LiteralsBufferMuxState { raw_literals_valid: false, ..state }
)
} else if (sel_rle_literals) {
(
state.rle_literals_data,
LiteralsBufferMuxState { rle_literals_valid: false, ..state }
LiteralsBufferMuxState { rle_literals_valid: false, ..state }
)
} else if (sel_huff_literals) {
(
state.huff_literals_data,
LiteralsBufferMuxState { huff_literals_valid: false, ..state }
LiteralsBufferMuxState { huff_literals_valid: false, ..state }
)
} else {
(
Expand Down Expand Up @@ -393,7 +393,7 @@ proc LiteralsBufferWriter<
literals_r: chan<LiteralsData> in;

ram_comp_input_s: chan<RamWrRespHandlerData<RAM_ADDR_WIDTH>> out;
ram_comp_output_r: chan<HistoryBufferPtr<RAM_ADDR_WIDTH>> in;
ram_comp_output_r: chan<RamWrRespHandlerResp<RAM_ADDR_WIDTH>> in;

buffer_sync_r: chan<LiteralsBufferReaderToWriterSync> in;
buffer_sync_s: chan<LiteralsBufferWriterToReaderSync> out;
Expand Down Expand Up @@ -429,7 +429,7 @@ proc LiteralsBufferWriter<
wr_resp_m7_r: chan<WriteResp> in
) {
let (ram_comp_input_s, ram_comp_input_r) = chan<RamWrRespHandlerData<RAM_ADDR_WIDTH>, u32:1>("ram_comp_input");
let (ram_comp_output_s, ram_comp_output_r) = chan<HistoryBufferPtr<RAM_ADDR_WIDTH>, u32:1>("ram_comp_output");
let (ram_comp_output_s, ram_comp_output_r) = chan<RamWrRespHandlerResp<RAM_ADDR_WIDTH>, u32:1>("ram_comp_output");

spawn parallel_rams::RamWrRespHandler<RAM_ADDR_WIDTH, RAM_DATA_WIDTH>(
ram_comp_input_r, ram_comp_output_s,
Expand All @@ -454,7 +454,6 @@ proc LiteralsBufferWriter<
State {
hyp_ptr: INIT_HB_PTR,
hb_len: INIT_HB_LENGTH as uN[RAM_ADDR_WIDTH + RAM_NUM_WIDTH],
prev_wr_comp: INIT_HB_PTR,
..zero!<State>()
}
}
Expand All @@ -476,7 +475,7 @@ proc LiteralsBufferWriter<
// read literals
let do_recv_literals = state.hb_len as u32 < HISTORY_BUFFER_SIZE_KB << u32:10;

let (tok1, literals_data) = recv_if(tok0, literals_r, do_recv_literals, zero!<LiteralsData>());
let (tok1, literals_data, literals_data_valid) = recv_if_non_blocking(tok0, literals_r, do_recv_literals, zero!<LiteralsData>());

// write literals to RAM
let packet_data = for (i, data): (u32, LiteralsWithLast) in range(u32:0, RAM_NUM) {
Expand All @@ -499,7 +498,7 @@ proc LiteralsBufferWriter<
let hb_add = packet.length as HistoryBufferLength;
let new_hb_len = std::mod_pow2(state.hb_len + hb_add, RAM_SIZE_TOTAL as HistoryBufferLength);

let write_reqs = if (do_recv_literals) {
let write_reqs = if (literals_data_valid) {
write_reqs
} else {
ZERO_WRITE_REQS
Expand All @@ -523,18 +522,10 @@ proc LiteralsBufferWriter<

let tok3_0 = send_if(tok2, ram_comp_input_s, do_write, wr_resp_handler_data);

let (tok3_1, comp_data, comp_data_valid) = recv_non_blocking(tok2, ram_comp_output_r, zero!<HistoryBufferPtr>());

// update RAM literals count
let literals_diff = (comp_data.number - state.prev_wr_comp.number) as LitLength;
let literals_diff = if (literals_diff == LitLength:0) {
LitLength:8
} else {
literals_diff
};
let (tok3_1, comp_data, comp_data_valid) = recv_non_blocking(tok2, ram_comp_output_r, zero!<RamWrRespHandlerResp>());

// update state
let state = if (do_recv_literals) {
let state = if (literals_data_valid) {
State {
hyp_ptr: new_hyp_ptr,
hb_len: new_hb_len,
Expand All @@ -545,9 +536,9 @@ proc LiteralsBufferWriter<
};

let state = if (comp_data_valid) {
trace_fmt!("COMP {:#x}", comp_data);
State {
literals_in_ram: state.literals_in_ram + literals_diff as uN[RAM_ADDR_WIDTH + std::clog2(RAM_NUM)],
prev_wr_comp: comp_data,
literals_in_ram: state.literals_in_ram + comp_data.length as uN[RAM_ADDR_WIDTH + std::clog2(RAM_NUM)],
..state
}
} else {
Expand All @@ -568,7 +559,7 @@ proc LiteralsBufferWriter<
let tok3 = join(tok3_0, tok3_1);

let sync_data = LiteralsBufferWriterToReaderSync<RAM_ADDR_WIDTH> {
literals_written: literals_diff,
literals_written: comp_data.length,
};
let tok4 = send_if(tok3, buffer_sync_s, comp_data_valid, sync_data);

Expand Down
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