[XLS] Enable internal FIFO materialization for several examples

We currently require an external FIFO definition by default, and these targets only passed due to not requiring a definition for depth-0 FIFOs before commit 4b262b0 We're planning to land a more batteries-included solution soon. PiperOrigin-RevId: 711868494
google · Jan 3, 2025 · 9dfd0b4 · 9dfd0b4
1 parent 5b55c5d
commit 9dfd0b4
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diff --git a/xls/examples/BUILD b/xls/examples/BUILD
@@ -834,6 +834,7 @@ xls_ir_verilog(
         "streaming_channel_ready_suffix": "_ready",
         "streaming_channel_valid_suffix": "_valid",
         "use_system_verilog": "true",
+        "materialize_internal_fifos": "true",
     },
     verilog_file = "delay.sv",
 )

diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD
@@ -386,6 +386,7 @@ mem_reader_codegen_args = common_codegen_args | {
     "flop_inputs_kind": "skid",
     "flop_outputs_kind": "skid",
     "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS,
+    "materialize_internal_fifos": "true",
 }
 
 xls_dslx_verilog(
@@ -440,6 +441,7 @@ mem_reader_adv_codegen_args = common_codegen_args | {
     "flop_inputs_kind": "skid",
     "flop_outputs_kind": "skid",
     "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS,
+    "materialize_internal_fifos": "true",
 }
 
 xls_dslx_verilog(
@@ -668,6 +670,7 @@ mem_writer_codegen_args = common_codegen_args | {
     "flop_inputs_kind": "skid",
     "flop_outputs_kind": "skid",
     "worst_case_throughput": "1",
+    "materialize_internal_fifos": "true",
 }
 
 xls_dslx_verilog(