Enhance build target, add RV IP core specific features

.cargo/config.toml

@@ -7,6 +7,12 @@ target = "riscv32imafc-unknown-none-elf"
 runner = "probe-rs run --chip HPM5361 --protocol jtag"
 
 rustflags = [
+    # Target features:
+    # The default for imacf is is "+m,+a,+c,+f"
+    # HPM6xxx does not have B extension
+    "-C",
+    "target-feature=+d,+zba,+zbb,+zbc,+zbs",
+    # Linker scripts:
     "-C",
     "link-arg=-Tmemory.x",
     "-C",

examples/blinky.rs

@@ -2,19 +2,20 @@
 #![no_std]
 
 use embedded_hal::delay::DelayNs;
-use hpm_hal::gpio::{Level, Output, Speed};
+use hal::gpio::{Level, Output, Speed};
 use riscv::delay::McycleDelay;
 use {defmt_rtt as _, hpm_hal as hal, panic_halt as _, riscv_rt as _};
 
-#[riscv_rt::entry]
+#[hal::entry]
 fn main() -> ! {
     let p = hal::init(Default::default());
 
     let mut delay = McycleDelay::new(hal::sysctl::clocks().hart0.0);
 
     defmt::info!("Board init!");
 
-    let mut led = Output::new(p.PA23, Level::Low, Speed::default());
+    let mut led = Output::new(p.PA10, Level::Low, Speed::default());
+    // let mut led = Output::new(p.PA23, Level::Low, Speed::default());
 
     loop {
         defmt::info!("tick");

examples/i2c_oled.rs

@@ -291,12 +291,33 @@ static mut UART: Option<hal::uart::Uart<'static, Blocking>> = None;
 
 #[hal::entry]
 fn main() -> ! {
-    let p = hal::init(Default::default());
+    let mut config = hal::Config::default();
+    {
+        use hal::sysctl::*;
+
+        // 24MHz * 40 = 960MHz
+        // PLL0CLK0 = 960 M
+        // PLL0CLK1 = 960 / 1.6 = 600 M
+        // PLL0CLK2 = 960 / 2.4 = 400 M
+        config.sysctl.pll0 = Some(Pll {
+            mfi: 40,
+            mfn: 0,
+            mfd: 240000000,
+            div: (0, 3, 7), // 960, 600, 400
+        });
+        // CPU0 = PLL0CLK0 / 2 = 480 M
+        // AHB = CPU0 / 3 = 160 M
+        config.sysctl.cpu0 = ClockConfig::new(ClockMux::PLL0CLK0, 2);
+        config.sysctl.ahb_div = AHBDiv::DIV3;
+    }
+
+    defmt::info!("Board preinit!");
+    let p = hal::init(config);
 
     let mut delay = McycleDelay::new(hal::sysctl::clocks().hart0.0);
 
     let uart_config = hal::uart::Config::default();
-    let mut uart = hal::uart::Uart::new_blocking(p.UART0, p.PA01, p.PA00, uart_config).unwrap();
+    let uart = hal::uart::Uart::new_blocking(p.UART0, p.PA01, p.PA00, uart_config).unwrap();
 
     unsafe {
         UART = Some(uart);
@@ -312,6 +333,12 @@ fn main() -> ! {
     writeln!(uart, "Clock summary:").unwrap();
     writeln!(uart, "  CPU0:\t{}Hz", hal::sysctl::clocks().hart0.0).unwrap();
     writeln!(uart, "  AHB:\t{}Hz", hal::sysctl::clocks().ahb.0).unwrap();
+    writeln!(
+        uart,
+        "  XPI0:\t{}Hz",
+        hal::sysctl::clocks().get_clock_freq(hal::pac::clocks::XPI0).0
+    )
+    .unwrap();
     writeln!(
         uart,
         "  I2C2:\t{}Hz",

src/gpio/input_future.rs

@@ -9,52 +9,56 @@ use super::{AnyPin, Flex, Input, Pin as GpioPin, SealedPin};
 use crate::interrupt::InterruptExt;
 use crate::{interrupt, pac};
 
+// PA00 to PA31
+const GPIO_LINES: usize = 32;
+
 const NEW_AW: AtomicWaker = AtomicWaker::new();
-static PORT_WAKERS: [AtomicWaker; 32] = [NEW_AW; 32];
+static PORT_WAKERS: [AtomicWaker; GPIO_LINES] = [NEW_AW; GPIO_LINES];
 
-// PA, PB, PX, PY
-const PORTS: &[usize] = &[0, 1, 0xD, 0xE];
+const PA: usize = 0;
+const PB: usize = 1;
+const PX: usize = 0xD;
+const PY: usize = 0xE;
 
 #[no_mangle]
 #[link_section = ".fast"]
 unsafe extern "riscv-interrupt-m" fn GPIO0_A() {
-    on_interrupt();
+    on_interrupt(PA);
 
     compiler_fence(Ordering::SeqCst);
     interrupt::GPIO0_A.complete();
 }
 #[no_mangle]
 #[link_section = ".fast"]
 unsafe extern "riscv-interrupt-m" fn GPIO0_B() {
-    on_interrupt();
+    on_interrupt(PB);
 
     compiler_fence(Ordering::SeqCst);
     interrupt::GPIO0_B.complete();
 }
 #[no_mangle]
 #[link_section = ".fast"]
 unsafe extern "riscv-interrupt-m" fn GPIO0_X() {
-    on_interrupt();
+    on_interrupt(PX);
 
     compiler_fence(Ordering::SeqCst);
     interrupt::GPIO0_X.complete();
 }
 #[no_mangle]
 #[link_section = ".fast"]
 unsafe extern "riscv-interrupt-m" fn GPIO0_Y() {
-    on_interrupt();
+    on_interrupt(PY);
 
     compiler_fence(Ordering::SeqCst);
     interrupt::GPIO0_Y.complete();
 }
 
-unsafe fn on_interrupt() {
-    for &port in PORTS {
-        for pin in BitIter(pac::GPIO0.if_(port).value().read().irq_flag()) {
-            pac::GPIO0.if_(port).value().write(|w| w.set_irq_flag(1 << pin)); // W1C
-            pac::GPIO0.ie(port).clear().write(|w| w.set_irq_en(1 << pin));
-            PORT_WAKERS[pin as usize].wake();
-        }
+#[inline]
+unsafe fn on_interrupt(port: usize) {
+    for pin in BitIter(pac::GPIO0.if_(port).value().read().irq_flag()) {
+        pac::GPIO0.if_(port).value().write(|w| w.set_irq_flag(1 << pin)); // W1C
+        pac::GPIO0.ie(port).clear().write(|w| w.set_irq_en(1 << pin));
+        PORT_WAKERS[pin as usize].wake();
     }
 }