This is the first processor I designed, a 5 stage in-order MIPS-ish RISC. It features direct mapped L1 instruction and data caches, and branch prediction

The implementation is not very good, and is mostly preserved here for posterity. I made a number of mistakes in this design:
- The contents of the data cache are modeled as having a single read/write port.  Because of the way tag lookup occurs, this means it can't perform a write immediately after a read because there is contention for the port.  There is a bunch of logic in the issue stage to schedule around this condition.
- I started the design purely structural, which was unnecessary and harder to read.
- Many of the SRAMs are modeled as async read (including the register file).  This precludes using the built-in block RAM resources, using more area, and slows down the max clock rate.