Merge pull request #1 from ThinkOpenly/JSON

Changes

.github/workflows/unicode-check.yml

@@ -0,0 +1,22 @@
+name: Unicode check
+on:
+  pull_request:
+    branches:
+      - JSON
+  push:
+    branches:
+      - JSON
+
+jobs:
+  check-unicode:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout code
+        uses: actions/checkout@v2
+
+      - name: Check for unicode in sail files
+        run: |
+          if git diff --exit-code --name-only ${{ github.base_ref }}..${{ github.head_ref }} | grep -E '\.sail$' | xargs grep -Pl "[\u2200-\u22FF]" --null --files-with-matches; then
+          echo "Error: Found unicode characters in Sail code"
+          exit 1
+          fi

model/riscv_insts_zba.sail

@@ -7,6 +7,7 @@
 /*=======================================================================================*/
 
 /* ****************************************************************** */
+$[name "Shift-left unsigned word (Immediate)"]
 union clause ast = RISCV_SLLIUW : (bits(6), regidx, regidx)
 
 mapping clause encdec = RISCV_SLLIUW(shamt, rs1, rd) if extension("Zba") & sizeof(xlen) == 64
@@ -38,9 +39,13 @@ mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_SH3ADDUW) if extension("
   <-> 0b0010000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0111011 if extension("Zba") & sizeof(xlen) == 64
 
 mapping zba_rtypeuw_mnemonic : bropw_zba <-> string = {
+  $[name "Add unsigned word"]
   RISCV_ADDUW    <-> "add.uw",
+  $[name "Shift unsigned word left by 1 and add"]
   RISCV_SH1ADDUW <-> "sh1add.uw",
+  $[name "Shift unsigned word left by 2 and add"]
   RISCV_SH2ADDUW <-> "sh2add.uw",
+  $[name "Shift unsigned word left by 3 and add"]
   RISCV_SH3ADDUW <-> "sh3add.uw"
 }
 
@@ -72,8 +77,11 @@ mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, RISCV_SH3ADD) if extension("Zba"
   <-> 0b0010000 @ rs2 @ rs1 @ 0b110 @ rd @ 0b0110011 if extension("Zba")
 
 mapping zba_rtype_mnemonic : brop_zba <-> string = {
+  $[name "Shift left by 1 and add"]
   RISCV_SH1ADD <-> "sh1add",
+  $[name "Shift left by 2 and add"]
   RISCV_SH2ADD <-> "sh2add",
+  $[name "Shift left by 3 and add"]
   RISCV_SH3ADD <-> "sh3add"
 }
 

model/riscv_insts_zbb.sail

@@ -7,6 +7,7 @@
 /*=======================================================================================*/
 
 /* ****************************************************************** */
+$[name "Rotate right Word (Immediate)"]
 union clause ast = RISCV_RORIW : (bits(5), regidx, regidx)
 
 mapping clause encdec = RISCV_RORIW(shamt, rs1, rd) if (extension("Zbb") | extension("Zbkb")) & sizeof(xlen) == 64
@@ -23,6 +24,7 @@ function clause execute (RISCV_RORIW(shamt, rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Rotate right (Immediate)"]
 union clause ast = RISCV_RORI : (bits(6), regidx, regidx)
 
 mapping clause encdec = RISCV_RORI(shamt, rs1, rd) if (extension("Zbb") | extension("Zbkb")) & (sizeof(xlen) == 64 | shamt[5] == bitzero)
@@ -50,7 +52,9 @@ mapping clause encdec = ZBB_RTYPEW(rs2, rs1, rd, RISCV_RORW) if (extension("Zbb"
   <-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011 if (extension("Zbb") | extension("Zbkb")) & sizeof(xlen) == 64
 
 mapping zbb_rtypew_mnemonic : bropw_zbb <-> string = {
+  $[name "Rotate Left Word (Register)"]
   RISCV_ROLW <-> "rolw",
+  $[name "Rotate right Word (Register)"]
   RISCV_RORW <-> "rorw"
 }
 
@@ -99,14 +103,23 @@ mapping clause encdec = ZBB_RTYPE(rs2, rs1, rd, RISCV_ROR) if extension("Zbb") |
   <-> 0b0110000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0110011 if extension("Zbb") | extension("Zbkb")
 
 mapping zbb_rtype_mnemonic : brop_zbb <-> string = {
+  $[name "AND with inverted operand"]
   RISCV_ANDN <-> "andn",
+  $[name "OR with inverted operand"]
   RISCV_ORN  <-> "orn",
+  $[name "Exclusive NOR"]
   RISCV_XNOR <-> "xnor",
+  $[name "Maximum"]
   RISCV_MAX  <-> "max",
+  $[name "Unsigned maximum"]
   RISCV_MAXU <-> "maxu",
+  $[name "Minimum"]
   RISCV_MIN  <-> "min",
+  $[name "Unsigned minimum"]
   RISCV_MINU <-> "minu",
+  $[name "Rotate left (Register)"]
   RISCV_ROL  <-> "rol",
+  $[name "Rotate right (Register)"]
   RISCV_ROR  <-> "ror"
 }
 
@@ -151,8 +164,11 @@ mapping clause encdec = ZBB_EXTOP(rs1, rd, RISCV_ZEXTH) if extension("Zbb") & si
   <-> 0b0000100 @ 0b00000 @ rs1 @ 0b100 @ rd @ 0b0111011 if extension("Zbb") & sizeof(xlen) == 64
 
 mapping zbb_extop_mnemonic : extop_zbb <-> string = {
+  $[name "Sign-extend byte"]
   RISCV_SEXTB <-> "sext.b",
+  $[name "Sign-extend halfword"]
   RISCV_SEXTH <-> "sext.h",
+  $[name "Zero-extend halfword"]
   RISCV_ZEXTH <-> "zext.h"
 }
 
@@ -171,6 +187,7 @@ function clause execute (ZBB_EXTOP(rs1, rd, op)) = {
 }
 
 /* ****************************************************************** */
+$[name "Byte-reverse register"]
 union clause ast = RISCV_REV8 : (regidx, regidx)
 
 mapping clause encdec = RISCV_REV8(rs1, rd) if (extension("Zbb") | extension("Zbkb")) & sizeof(xlen) == 32
@@ -192,6 +209,7 @@ function clause execute (RISCV_REV8(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Bitwise OR-Combine, byte granule"]
 union clause ast = RISCV_ORCB : (regidx, regidx)
 
 mapping clause encdec = RISCV_ORCB(rs1, rd) if extension("Zbb")
@@ -212,6 +230,7 @@ function clause execute (RISCV_ORCB(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Count set bits"]
 union clause ast = RISCV_CPOP : (regidx, regidx)
 
 mapping clause encdec = RISCV_CPOP(rs1, rd) if extension("Zbb")
@@ -230,6 +249,7 @@ function clause execute (RISCV_CPOP(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Count set bits in word"]
 union clause ast = RISCV_CPOPW : (regidx, regidx)
 
 mapping clause encdec = RISCV_CPOPW(rs1, rd) if extension("Zbb") & sizeof(xlen) == 64
@@ -248,6 +268,7 @@ function clause execute (RISCV_CPOPW(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Count leading zero bits"]
 union clause ast = RISCV_CLZ : (regidx, regidx)
 
 mapping clause encdec = RISCV_CLZ(rs1, rd) if extension("Zbb")
@@ -269,6 +290,7 @@ function clause execute (RISCV_CLZ(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Count leading zero bits in word"]
 union clause ast = RISCV_CLZW : (regidx, regidx)
 
 mapping clause encdec = RISCV_CLZW(rs1, rd) if extension("Zbb") & sizeof(xlen) == 64
@@ -290,6 +312,7 @@ function clause execute (RISCV_CLZW(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Count trailing zero bits"]
 union clause ast = RISCV_CTZ : (regidx, regidx)
 
 mapping clause encdec = RISCV_CTZ(rs1, rd) if extension("Zbb")
@@ -311,6 +334,7 @@ function clause execute (RISCV_CTZ(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Count trailing zero bits in word"]
 union clause ast = RISCV_CTZW : (regidx, regidx)
 
 mapping clause encdec = RISCV_CTZW(rs1, rd) if extension("Zbb") & sizeof(xlen) == 64

model/riscv_insts_zbc.sail

@@ -7,6 +7,7 @@
 /*=======================================================================================*/
 
 /* ****************************************************************** */
+$[name "Carry-less multiply (low-part)"]
 union clause ast = RISCV_CLMUL : (regidx, regidx, regidx)
 
 mapping clause encdec = RISCV_CLMUL(rs2, rs1, rd) if extension("Zbc") | extension("Zbkc")
@@ -26,6 +27,7 @@ function clause execute (RISCV_CLMUL(rs2, rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Carry-less multiply (high-part)"]
 union clause ast = RISCV_CLMULH : (regidx, regidx, regidx)
 
 mapping clause encdec = RISCV_CLMULH(rs2, rs1, rd) if extension("Zbc") | extension("Zbkc")
@@ -45,6 +47,7 @@ function clause execute (RISCV_CLMULH(rs2, rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Carry-less multiply (reversed)"]
 union clause ast = RISCV_CLMULR : (regidx, regidx, regidx)
 
 mapping clause encdec = RISCV_CLMULR(rs2, rs1, rd) if extension("Zbc")

model/riscv_insts_zbkb.sail

@@ -16,7 +16,9 @@ mapping clause encdec = ZBKB_RTYPE(rs2, rs1, rd, RISCV_PACKH) if extension("Zbkb
   <-> 0b0000100 @ rs2 @ rs1 @ 0b111 @ rd @ 0b0110011 if extension("Zbkb")
 
 mapping zbkb_rtype_mnemonic : brop_zbkb <-> string = {
+  $[name "Pack low halves of registers"]
   RISCV_PACK  <-> "pack",
+  $[name "Pack low bytes of registers"]
   RISCV_PACKH <-> "packh"
 }
 
@@ -35,6 +37,7 @@ function clause execute (ZBKB_RTYPE(rs2, rs1, rd, op)) = {
 }
 
 /* ****************************************************************** */
+$[name "Pack low 16-bits of registers (RV64)"]
 union clause ast = ZBKB_PACKW : (regidx, regidx, regidx)
 
 mapping clause encdec = ZBKB_PACKW(rs2, rs1, rd) if extension("Zbkb") & sizeof(xlen) == 64
@@ -53,6 +56,7 @@ function clause execute (ZBKB_PACKW(rs2, rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Bit interleave"]
 union clause ast = RISCV_ZIP : (regidx, regidx)
 
 mapping clause encdec = RISCV_ZIP(rs1, rd) if extension("Zbkb") & sizeof(xlen) == 32
@@ -74,6 +78,7 @@ function clause execute (RISCV_ZIP(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Bit deinterleave"]
 union clause ast = RISCV_UNZIP : (regidx, regidx)
 
 mapping clause encdec = RISCV_UNZIP(rs1, rd) if extension("Zbkb") & sizeof(xlen) == 32
@@ -95,6 +100,7 @@ function clause execute (RISCV_UNZIP(rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Reverse bits in bytes"]
 union clause ast = RISCV_BREV8 : (regidx, regidx)
 
 mapping clause encdec = RISCV_BREV8(rs1, rd) if extension("Zbkb")

model/riscv_insts_zbkx.sail

@@ -7,6 +7,7 @@
 /*=======================================================================================*/
 
 /* ****************************************************************** */
+$[name "Crossbar permutation (bytes)"]
 union clause ast = RISCV_XPERM8 : (regidx, regidx, regidx)
 
 mapping clause encdec = RISCV_XPERM8(rs2, rs1, rd) if extension("Zbkx")
@@ -30,6 +31,7 @@ function clause execute (RISCV_XPERM8(rs2, rs1, rd)) = {
 }
 
 /* ****************************************************************** */
+$[name "Crossbar permutation (nibbles)"]
 union clause ast = RISCV_XPERM4 : (regidx, regidx, regidx)
 
 mapping clause encdec = RISCV_XPERM4(rs2, rs1, rd) if extension("Zbkx")

model/riscv_insts_zbs.sail

@@ -22,9 +22,13 @@ mapping clause encdec = ZBS_IOP(shamt, rs1, rd, RISCV_BSETI) if extension("Zbs")
   <-> 0b001010 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if extension("Zbs") & (sizeof(xlen) == 64 | shamt[5] == bitzero)
 
 mapping zbs_iop_mnemonic : biop_zbs <-> string = {
+  $[name "Single-Bit Clear (Immediate)"]
   RISCV_BCLRI <-> "bclri",
+  $[name "Single-Bit Extract (Immediate)"]
   RISCV_BEXTI <-> "bexti",
+  $[name "Single-Bit Invert (Immediate)"]
   RISCV_BINVI <-> "binvi",
+  $[name "Single-Bit Set (Immediate)"]
   RISCV_BSETI <-> "bseti"
 }
 
@@ -62,9 +66,13 @@ mapping clause encdec = ZBS_RTYPE(rs2, rs1, rd, RISCV_BSET) if extension("Zbs")
   <-> 0b0010100 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0110011 if extension("Zbs")
 
 mapping zbs_rtype_mnemonic : brop_zbs <-> string = {
+  $[name "Single-Bit Clear (Register)"]
   RISCV_BCLR    <-> "bclr",
+  $[name "Single-Bit Extract (Register)"]
   RISCV_BEXT    <-> "bext",
+  $[name "Single-Bit Invert (Register)"]
   RISCV_BINV    <-> "binv",
+  $[name "Single-Bit Set (Register)"]
   RISCV_BSET    <-> "bset"
 }
 

model/riscv_insts_zkn.sail

@@ -79,6 +79,7 @@ function clause execute (SHA256SUM1(rs1, rd)) = {
  * ----------------------------------------------------------------------
  */
 
+$[name "AES middle round encrypt (RV32)"]
 union clause ast = AES32ESMI : (bits(2), regidx, regidx, regidx)
 
 mapping clause encdec = AES32ESMI (bs, rs2, rs1, rd) if extension("Zkne") & sizeof(xlen) == 32
@@ -99,6 +100,7 @@ function clause execute (AES32ESMI (bs, rs2, rs1, rd)) = {
   RETIRE_SUCCESS
 }
 
+$[name "AES final round encrypt (RV32)"]
 union clause ast = AES32ESI : (bits(2), regidx, regidx, regidx)
 
 mapping clause encdec = AES32ESI (bs, rs2, rs1, rd) if extension("Zkne") & sizeof(xlen) == 32
@@ -123,6 +125,7 @@ function clause execute (AES32ESI (bs, rs2, rs1, rd)) = {
  * ----------------------------------------------------------------------
  */
 
+$[name "AES middle round decrypt (RV32)"]
 union clause ast = AES32DSMI : (bits(2), regidx, regidx, regidx)
 
 mapping clause encdec = AES32DSMI (bs, rs2, rs1, rd) if extension("Zknd") & sizeof(xlen) == 32
@@ -143,6 +146,7 @@ function clause execute (AES32DSMI (bs, rs2, rs1, rd)) = {
   RETIRE_SUCCESS
 }
 
+$[name "AES final round decrypt (RV32)"]
 union clause ast = AES32DSI  : (bits(2), regidx, regidx, regidx)
 
 mapping clause encdec = AES32DSI (bs, rs2, rs1, rd) if extension("Zknd") & sizeof(xlen) == 32
@@ -258,12 +262,19 @@ function clause execute (SHA512SUM1R(rs2, rs1, rd)) = {
  * ----------------------------------------------------------------------
  */
 
+$[name "AES Key Schedule Instruction 1 (RV64)"]
 union clause ast = AES64KS1I : (bits(4), regidx, regidx)
+$[name "AES Key Schedule Instruction 2 (RV64)"]
 union clause ast = AES64KS2  : (regidx, regidx, regidx)
+$[name "AES Decrypt KeySchedule MixColumns (RV64)"]
 union clause ast = AES64IM   : (regidx, regidx)
+$[name "AES encrypt middle round instruction (RV64)"]
 union clause ast = AES64ESM  : (regidx, regidx, regidx)
+$[name "AES encrypt final round instruction (RV64)"]
 union clause ast = AES64ES   : (regidx, regidx, regidx)
+$[name "AES decrypt middle round (RV64)"]
 union clause ast = AES64DSM  : (regidx, regidx, regidx)
+$[name "AES decrypt final round (RV64)"]
 union clause ast = AES64DS   : (regidx, regidx, regidx)
 
 mapping clause encdec = AES64KS1I (rnum, rs1, rd) if (extension("Zkne") | extension("Zknd")) & (sizeof(xlen) == 64) & (rnum <_u 0xB)