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Merge pull request #1 from kalhorghazal/forwarding
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Add forwarding
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@kalhorghazal
kalhorghazal authored Feb 6, 2021
2 parents bc2bbe2 + 2fa3377 commit d53a53d
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Showing 10 changed files with 188 additions and 35 deletions.
49 changes: 43 additions & 6 deletions ARM.v
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@
module ARM
(
input clk,
input rst
input rst,
input enableForwarding
);

wire [`WORD_WIDTH-1:0] IF_stage_pc_out;
Expand Down Expand Up @@ -96,6 +97,7 @@ module ARM
ID_reg_Imm_out,
ID_reg_B_out,
ID_reg_SR_update_out;
wire [`REG_FILE_DEPTH-1:0] ID_reg_reg_file_src1, ID_reg_reg_file_src2;

ID_Reg ID_Reg_Inst(
.clk(clk),
Expand All @@ -113,6 +115,8 @@ module ARM
.Imm_in(ID_stage_Imm_out),
.B_in(ID_stage_B_out),
.SR_update_in(ID_stage_SR_update_out),
.reg_file_src1_in(ID_stage_reg_file_src1),
.reg_file_src2_in(ID_stage_reg_file_src2),
.pc(ID_reg_pc_out),
.instruction(ID_reg_instruction_out),
.reg_file_dst_out(ID_reg_reg_file_dst_out),
Expand All @@ -126,21 +130,30 @@ module ARM
.B_out(ID_reg_B_out),
.SR_update_out(ID_reg_SR_update_out),
.status_register_in(status),
.status_register_out(ID_reg_SR_out)
.status_register_out(ID_reg_SR_out),
.reg_file_src1_out(ID_reg_reg_file_src1),
.reg_file_src2_out(ID_reg_reg_file_src2)
);

wire [`WORD_WIDTH-1:0] EXE_stage_pc_out;
wire [`WORD_WIDTH-1:0] EXE_stage_instruction_out;
wire [`REG_FILE_DEPTH-1:0] EXE_stage_reg_file_dst_out;
wire [`WORD_WIDTH-1:0] EXE_stage_val_Rm_out;
wire [3:0] EXE_stage_SR_out;
wire [`WORD_WIDTH-1:0] ALU_res;
wire EXE_stage_mem_read_out, EXE_stage_mem_write_out,
EXE_stage_WB_en_out;

wire [1:0] EXE_sel_src1, EXE_sel_src2;
wire [`WORD_WIDTH-1:0] Mem_Stage_ALU_res_out;

EXE_Stage EXE_Stage_Inst(
.clk(clk),
.rst(rst),
.pc_in(ID_reg_pc_out),
.instruction_in(ID_reg_instruction_out),
.MEM_stage_val(Mem_Stage_ALU_res_out),
.WB_stage_val(WB_Value),
.signed_immediate(ID_reg_signed_immediate_out),
.EX_command(ID_reg_EX_command_out),
.SR_in(ID_reg_SR_out),
Expand All @@ -151,16 +164,24 @@ module ARM
.WB_en_in(ID_reg_WB_en_out),
.B_in(ID_reg_B_out),
.val_Rn_in(ID_reg_val_Rn_out), .val_Rm_in(ID_reg_val_Rm_out),

.sel_src1(EXE_sel_src1),
.sel_src2(EXE_sel_src2),

.dst_out(EXE_stage_reg_file_dst_out),
.SR_out(EXE_stage_SR_out),
.ALU_res(ALU_res),
.val_Rm_out(EXE_stage_val_Rm_out),
.branch_address(branch_address),
.mem_read_out(EXE_stage_mem_read_out), .mem_write_out(EXE_stage_mem_write_out),
.WB_en_out(EXE_stage_WB_en_out),
.B_out(EXE_stage_B_out)
.B_out(EXE_stage_B_out),
.pc(EXE_stage_pc_out),
.instruction(EXE_stage_instruction_out)
);

wire [`WORD_WIDTH-1:0] EXE_reg_pc_out;
wire [`WORD_WIDTH-1:0] EXE_reg_instruction_out;
wire [`REG_FILE_DEPTH-1:0] EXE_reg_dst_out;
wire [`WORD_WIDTH-1:0] EXE_reg_ALU_res_out;
wire [`WORD_WIDTH-1:0] EXE_reg_val_Rm_out;
Expand All @@ -169,6 +190,8 @@ module ARM
EXE_Reg EXE_Reg_Inst(
.clk(clk),
.rst(rst),
.pc_in(EXE_stage_pc_out),
.instruction_in(EXE_stage_instruction_out),
.dst_in(EXE_stage_reg_file_dst_out),
.mem_read_in(EXE_stage_mem_read_out), .mem_write_in(EXE_stage_mem_write_out),
.WB_en_in(EXE_stage_WB_en_out),
Expand All @@ -178,11 +201,12 @@ module ARM
.ALU_res_out(EXE_reg_ALU_res_out),
.val_Rm_out(EXE_reg_val_Rm_out),
.mem_read_out(EXE_reg_mem_read_out), .mem_write_out(EXE_reg_mem_write_out),
.WB_en_out(EXE_reg_WB_en_out)
.WB_en_out(EXE_reg_WB_en_out),
.pc(EXE_reg_pc_out),
.instruction(EXE_reg_instruction_out)
);

wire [`REG_FILE_DEPTH-1:0] Mem_Stage_dst_out;
wire [`WORD_WIDTH-1:0] Mem_Stage_ALU_res_out;
wire [`WORD_WIDTH-1:0] Mem_Stage_mem_out;
wire Mem_Stage_read_out, Mem_Stage_WB_en_out;

Expand Down Expand Up @@ -250,16 +274,29 @@ module ARM
wire[`REG_FILE_DEPTH-1:0] MEM_dest = EXE_reg_dst_out;

Hazard_Detection_Unit Hazard_Detection_Unit_Inst(
.enableForwarding(enableForwarding),
.src1(ID_stage_reg_file_src1),
.src2(ID_stage_reg_file_src2),
.EXE_dest(EXE_dest),
.MEM_dest(MEM_dest),
.EXE_WB_en(EXE_WB_en),
.MEM_WB_en(MEM_WB_en),
.EXE_memread_en(EXE_stage_mem_read_out),
.has_src1(has_src1),
.has_src2(has_src2),
.hazard_detected(hazard_detected)
);

endmodule
Forwarding_Unit Forwarding_Unit_Inst(
.enable(enableForwarding),
.src1(ID_reg_reg_file_src1),
.src2(ID_reg_reg_file_src2),
.MEM_dest(MEM_dest),
.WB_dest(WB_Stage_dst_out),
.MEM_WB_en(MEM_WB_en),
.WB_WB_en(WB_Stage_WB_en_out),
.sel_src1(EXE_sel_src1),
.sel_src2(EXE_sel_src2)
);

endmodule
7 changes: 5 additions & 2 deletions ARM_TB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,13 @@ module ARM_TB;

reg clk;
reg rst;
reg enableForwarding;


ARM CPU(
.clk(clk),
.rst(rst)
.rst(rst),
.enableForwarding(enableForwarding)
);

initial begin
Expand All @@ -18,10 +20,11 @@ module ARM_TB;
end

initial begin
enableForwarding = 1;
rst = 1;
# (clock_period / 2);
rst = 0;
# (600*clock_period);
# (1000*clock_period);
$stop;
end
endmodule
4 changes: 2 additions & 2 deletions Control_Unit.v
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Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ module Control_Unit
end

assign SR_update = S;
assign has_src1 = (EX_command == `EX_MOV ||
EX_command == `EX_MOV || B) ? 1'b0 : 1'b1;
assign has_src1 = ((EX_command == `EX_MOV) ||
(EX_command == `EX_MVN) || B) ? 1'b0 : 1'b1;

endmodule
10 changes: 9 additions & 1 deletion EXE_Reg.v
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Original file line number Diff line number Diff line change
Expand Up @@ -4,18 +4,24 @@ module EXE_Reg
(
input clk,
input rst,
input [`WORD_WIDTH-1:0] pc_in,
input [`WORD_WIDTH-1:0] instruction_in,
input [`REG_FILE_DEPTH-1:0] dst_in,
input mem_read_in, mem_write_in, WB_en_in,
input [`WORD_WIDTH-1:0] val_Rm_in,
input [`WORD_WIDTH-1:0] ALU_res_in,
output reg [`REG_FILE_DEPTH-1:0] dst_out,
output reg [`WORD_WIDTH-1:0] ALU_res_out,
output reg [`WORD_WIDTH-1:0] val_Rm_out,
output reg mem_read_out, mem_write_out, WB_en_out
output reg mem_read_out, mem_write_out, WB_en_out,
output reg [`WORD_WIDTH-1:0] pc,
output reg [`WORD_WIDTH-1:0] instruction
);

always @(posedge clk, posedge rst) begin
if(rst) begin
pc <= 0;
instruction <= 0;
dst_out <= 0;
ALU_res_out <= 0;
val_Rm_out <= 0;
Expand All @@ -24,6 +30,8 @@ always @(posedge clk, posedge rst) begin
WB_en_out <= 0;
end
else begin
pc <= pc_in;
instruction <= instruction_in;
dst_out <= dst_in;
ALU_res_out <= ALU_res_in;
val_Rm_out <= val_Rm_in;
Expand Down
33 changes: 29 additions & 4 deletions EXE_Stage.v
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Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,27 @@ module EXE_Stage
input rst,
input [`WORD_WIDTH-1:0] pc_in,
input [`WORD_WIDTH-1:0] instruction_in,
input [`WORD_WIDTH-1:0] MEM_stage_val,
input [`WORD_WIDTH-1:0] WB_stage_val,
input [`SIGNED_IMM_WIDTH-1:0] signed_immediate,
input [3:0] EX_command,
input [3:0] SR_in,
input [`SHIFTER_OPERAND_WIDTH-1:0] shifter_operand,
input [`REG_FILE_DEPTH-1:0] dst_in,
input mem_read_in, mem_write_in, imm, WB_en_in, B_in,
input [`WORD_WIDTH-1:0] val_Rn_in, val_Rm_in,

input [1:0] sel_src1,
input [1:0] sel_src2,

output [`REG_FILE_DEPTH-1:0] dst_out,
output [3:0] SR_out,
output [`WORD_WIDTH-1:0] ALU_res,
output [`WORD_WIDTH-1:0] val_Rm_out,
output [`WORD_WIDTH-1:0] branch_address,
output mem_read_out, mem_write_out, WB_en_out, B_out
output mem_read_out, mem_write_out, WB_en_out, B_out,
output [`WORD_WIDTH-1:0] pc,
output [`WORD_WIDTH-1:0] instruction
);

wire [`WORD_WIDTH-1:0] val2;
Expand All @@ -30,16 +38,31 @@ module EXE_Stage
.out(branch_address)
);

wire [`WORD_WIDTH-1:0] alu_src1;
wire [`WORD_WIDTH-1:0] alu_src2;

MUX_4_to_1 #(.WORD_WIDTH(`WORD_WIDTH)) MUX_ALU_sel1 (
.in1(val_Rn_in), .in2(MEM_stage_val), .in3(WB_stage_val), .in4(val_Rn_in),
.sel(sel_src1),
.out(alu_src1)
);

MUX_4_to_1 #(.WORD_WIDTH(`WORD_WIDTH)) MUX_ALU_sel2 (
.in1(val_Rm_in), .in2(MEM_stage_val), .in3(WB_stage_val), .in4(val_Rm_in),
.sel(sel_src2),
.out(alu_src2)
);

Val2_Generator Val2_Generator_Inst(
.val_Rm(val_Rm_in),
.val_Rm(alu_src2),
.shifter_operand(shifter_operand),
.imm(imm),
.is_for_memory(is_for_memory),
.val2_out(val2)
);

ALU ALU_Inst(
.val1(val_Rn_in),
.val1(alu_src1),
.val2(val2),
.EX_command(EX_command),
.carry(SR_in[2]),
Expand All @@ -48,11 +71,13 @@ module EXE_Stage
);

assign is_for_memory = mem_read_in | mem_write_in;
assign pc = pc_in;
assign instruction = instruction_in;
assign dst_out = dst_in;
assign mem_read_out = mem_read_in;
assign mem_write_out = mem_write_in;
assign WB_en_out = WB_en_in;
assign B_out = B_in;
assign val_Rm_out = val_Rm_in;
assign val_Rm_out = alu_src2;

endmodule
30 changes: 30 additions & 0 deletions Forwarding_Unit.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
`include "settings.h"

module Forwarding_Unit (
input enable,
input [`REG_FILE_DEPTH-1:0] src1,
input [`REG_FILE_DEPTH-1:0] src2,
input [`REG_FILE_DEPTH-1:0] MEM_dest,
input [`REG_FILE_DEPTH-1:0] WB_dest,
input MEM_WB_en,
input WB_WB_en,
output reg [1:0] sel_src1,
output reg [1:0] sel_src2
);

always @(*) begin
sel_src1 = `FORWARDING_SEL_NOP;
sel_src2 = `FORWARDING_SEL_NOP;
if(enable) begin
if ((src1 == MEM_dest) && (MEM_WB_en == 1'b1))
sel_src1 = `FORWARDING_SEL_MEM;
else if ((src1 == WB_dest) && (WB_WB_en == 1'b1))
sel_src1 = `FORWARDING_SEL_WB;
if ((src2 == MEM_dest) && (MEM_WB_en == 1'b1))
sel_src2 = `FORWARDING_SEL_MEM;
else if ((src2 == WB_dest) && (WB_WB_en == 1'b1))
sel_src2 = `FORWARDING_SEL_WB;
end
end

endmodule
45 changes: 28 additions & 17 deletions Hazard_Detection_Unit.v
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Original file line number Diff line number Diff line change
@@ -1,34 +1,45 @@
`include "settings.h"

module Hazard_Detection_Unit (
input enableForwarding,
input [`REG_FILE_DEPTH-1:0] src1,
input [`REG_FILE_DEPTH-1:0] src2,
input [`REG_FILE_DEPTH-1:0] EXE_dest,
input [`REG_FILE_DEPTH-1:0] MEM_dest,
input EXE_WB_en,
input MEM_WB_en,
input EXE_memread_en,
input has_src1,
input has_src2,
output reg hazard_detected
);

always @(*) begin
if ((src1 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
hazard_detected = 1'b1;
always @(*) begin
hazard_detected = 1'b0;
if(~enableForwarding) begin
if ((src1 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
hazard_detected = 1'b1;
end
else if ((src1 == MEM_dest) && (MEM_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
hazard_detected = 1'b1;
end
else if ((src2 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
hazard_detected = 1'b1;
end
else if ((src2 == MEM_dest) && (MEM_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
hazard_detected = 1'b1;
end
end
else if ((src1 == MEM_dest) && (MEM_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
hazard_detected = 1'b1;
end
else if ((src2 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
hazard_detected = 1'b1;
end
else if ((src2 == MEM_dest) && (MEM_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
hazard_detected = 1'b1;
end
else begin
hazard_detected = 1'b0;
end
end
else begin
if(EXE_memread_en) begin
if ((src1 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
hazard_detected = 1'b1;
end
else if ((src2 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
hazard_detected = 1'b1;
end
end
end
end

endmodule

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