various changes, moving repo to another pc

arch/vc4/arch.c

@@ -1,11 +1,32 @@
 #include <sys/types.h>
 #include <stdint.h>
 #include <lk/debug.h>
+#include <lk/console_cmd.h>
+#include <lk/reg.h>
+#include <platform/bcm28xx.h>
+
+static int cmd_boot_other_core(int argc, const cmd_args *argv);
+
+static char core2_stack[4096];
+uint32_t core2_stack_top = 0;
+
+STATIC_COMMAND_START
+STATIC_COMMAND("boot_other_core", "boot the 2nd vpu core", &cmd_boot_other_core)
+STATIC_COMMAND_END(arch);
 
 void arch_early_init(void) {
+  uint32_t r28, sp, sr;
+  __asm__ volatile ("mov %0, r28" : "=r"(r28));
+  __asm__ volatile ("mov %0, sp" : "=r"(sp));
+  __asm__ volatile ("mov %0, sr" : "=r"(sr));
+  dprintf(INFO, "arch_early_init\nr28: 0x%x\nsp: 0x%x\nsr: 0x%x\n", r28, sp, sr);
 }
 
 void arch_init(void) {
+  uint32_t r28, sp;
+  __asm__ volatile ("mov %0, r28" : "=r"(r28));
+  __asm__ volatile ("mov %0, sp" : "=r"(sp));
+  dprintf(INFO, "arch_init\nr28: 0x%x\nsp: 0x%x\n", r28, sp);
 }
 
 void arch_idle(void) {
@@ -16,3 +37,16 @@ void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3
     PANIC_UNIMPLEMENTED;
 }
 
+void core2_start();
+
+static int cmd_boot_other_core(int argc, const cmd_args *argv) {
+  core2_stack_top = (core2_stack + sizeof(core2_stack)) - 4;
+  *REG32(A2W_PLLC_CORE1) = A2W_PASSWORD | 6; // 3ghz/6 == 500mhz
+  *REG32(IC1_WAKEUP) = &core2_start;
+  return 0;
+}
+
+void core2_entry() {
+  dprintf(INFO, "core2 says hello\n");
+  for (;;);
+}

arch/vc4/intc.c

@@ -21,6 +21,8 @@ struct handlerArgPair irq_handlers[64];
 // if the highest bit on this addr is set, the cpu will switch into supervisor mode
 irqType __attribute__ ((aligned (512))) vectorTable[144]; // might only need to be 128 entries
 
+uint8_t irq_stack0[4096];
+
 static const char* g_ExceptionNames[] = {
   "Zero",
   "Misaligned",
@@ -50,6 +52,10 @@ void set_interrupt(int intno, bool enable, int core) {
 
 
 void intc_init(void) {
+  uint32_t r28, sp;
+  __asm__ volatile ("mov %0, r28" : "=r"(r28));
+  __asm__ volatile ("mov %0, sp" : "=r"(sp));
+  dprintf(INFO, "intc_init\nr28: 0x%x\nsp: 0x%x\n", r28, sp);
   // TODO
   for (int i=0; i<64; i++) {
     irq_handlers[0].h = 0; // is this needed? maybe .bss already took care of it?
@@ -77,18 +83,23 @@ void intc_init(void) {
   }
   // swi opcode handler
   for (int i=32; i<=63; i++) {
-    vectorTable[i] = fleh_irq;
+    vectorTable[i] = (uint32_t)fleh_irq | 1;
   }
   // external interrupts
   for (int i=64; i<=127; i++) {
-    vectorTable[i] = fleh_irq;
+    vectorTable[i] = (uint32_t)fleh_irq | 1;
   }
 
+  uint32_t irq_sp = (irq_stack0 + sizeof(irq_stack0)) - 4;
+  dprintf(INFO, "r28 = 0x%x\nirq_stack0: %p\nsizeof(irq_stack0): %d\n", irq_sp, irq_stack0, sizeof(irq_stack0));
+
+  __asm__ volatile ("mov r28, 0xdeadbeef": :"r"(irq_sp));
+
   *REG32(IC0_VADDR) = vectorTable;
   *REG32(IC1_VADDR) = vectorTable;
 
   if (*REG32(IC0_VADDR) != vectorTable) {
-    printf("vector table now at 0x%08lx 0x%08lx\n", *REG32(IC0_VADDR), (uint32_t)vectorTable);
+    printf("vector table now at 0x%08x 0x%08x\n", *REG32(IC0_VADDR), (uint32_t)vectorTable);
     panic("vector table failed to install");
   }
 }
@@ -182,11 +193,25 @@ void sleh_fatal(vc4_saved_state_t* pcb, uint32_t n) {
   while(true) __asm__ volatile ("nop");
 }
 
+// upon entry to this function(before its prologue runs), sp and r0 point to a `struct vc4_saved_state_t`
+// r0 (which lands in pcb) contains a copy of that sp from before the prologue
+// some common values and offsets:
+// r0 +   0: r23
+// ...
+// r0 +  92: r0
+// r0 +  96: lr
+// r0 + 100: sr
+// r0 + 104: pc
 void sleh_irq(vc4_saved_state_t* pcb, uint32_t tp) {
   uint32_t status = *REG32(IC0_S);
   uint32_t source = status & 0xFF;
-  uint32_t cs;
-  int ret;
+  enum handler_return ret = INT_NO_RESCHEDULE;
+
+  uint32_t r28, sp, sr;
+  __asm__ volatile ("mov %0, r28" : "=r"(r28));
+  __asm__ volatile ("mov %0, sp" : "=r"(sp));
+  __asm__ volatile ("mov %0, sr" : "=r"(sr));
+  //dprintf(INFO, "sleh_irq\nr28: 0x%x\nsp: 0x%x\nsr: 0x%x\n", r28, sp, sr);
 
   //dprintf(INFO, "VPU Received interrupt from source %d\n", source);
 
@@ -195,7 +220,11 @@ void sleh_irq(vc4_saved_state_t* pcb, uint32_t tp) {
   case 121: // uart
     assert(irq_handlers[source - 64].h);
     ret = irq_handlers[source - 64].h(irq_handlers[source - 64].arg);
-    if (ret == INT_RESCHEDULE) thread_preempt();
+    if (ret == INT_RESCHEDULE) {
+      //dprintf(INFO, "pre-emptying\n");
+      thread_preempt();
+      //dprintf(INFO, "done preempt\n");
+    }
     break;
   case INTERRUPT_ARM:
     // fired when the arm cpu writes to the arm->vpu mailbox

arch/vc4/interrupt.S

@@ -48,7 +48,6 @@ fleh_irq:
   SaveRegsAll
   mov r0, sp
   mov r1, r29
-  di
   bl sleh_irq
 return_from_exception:
   ldm r16-r23, (sp++)

arch/vc4/start.S

@@ -9,3 +9,14 @@ _start:
   bl lk_main
 loop:
   b loop
+
+.global core2_start
+core2_start:
+  mov r0, core2_stack_top
+  ld sp, (r0)
+  mov r0, 0
+  mov r1, 'A'
+  bl uart_putc
+  bl core2_entry
+loop2:
+  b loop2

arch/vc4/thread.c

@@ -4,6 +4,11 @@
 void vc4_context_switch(uint32_t *oldsp, uint32_t newsp);
 
 void arch_context_switch(thread_t *oldthread, thread_t *newthread) {
+  uint32_t r28, sp;
+  __asm__ volatile ("mov %0, r28" : "=r"(r28));
+  __asm__ volatile ("mov %0, sp" : "=r"(sp));
+  //dprintf(INFO, "arch_context_switch\nr28: 0x%x\nsp: 0x%x\n", r28, sp);
+  //dprintf(INFO, "switching (%s) -> %p(%s)\n", oldthread->name, newthread->arch.sp, newthread->name);
   vc4_context_switch(&oldthread->arch.sp, newthread->arch.sp);
 }
 
@@ -17,16 +22,23 @@ static inline void push(thread_t *t, uint32_t val) {
 static void initial_thread_func(void) __NO_RETURN;
 static void initial_thread_func(void) {
   thread_t *ct = get_current_thread();
+  uint32_t own_sp;
+
+  __asm__ volatile ("mov %0, sp": "=r"(own_sp));
+  dprintf(INFO, "thread %p(%s) starting with sp near 0x%x\n", ct, ct->name, own_sp);
 
   int ret = ct->entry(ct->arg);
 
   thread_exit(ret);
 }
 
 void arch_thread_initialize(thread_t *t) {
+  printf("thread %p(%s) has a stack of %p+0x%x\n", t, t->name, t->stack, t->stack_size);
   t->arch.sp = (t->stack + t->stack_size) - 4;
   push(t, &initial_thread_func);
-  push(t, 0); // the initial frame-pointer
+  for (int i=6; i<=23; i++) {
+    push(t, 0); // r${i}
+  }
 }
 
 void arch_dump_thread(thread_t *t) {

arch/vc4/thread_asm.S

@@ -3,7 +3,11 @@
 // r0 is address to save the sp to
 // r1 is the new sp to load
 vc4_context_switch:
-  stm r6,lr,(--sp)
+  stm lr, (--sp)
+  stm r6-r15, (--sp)
+  stm r16-r23, (--sp)
   st sp, (r0)
   mov sp, r1
-  ldm r6,pc,(sp++)
+  ldm r16-r23, (sp++)
+  ldm r6-r15, (sp++)
+  ldm pc,(sp++)

kernel/thread.c

@@ -461,6 +461,8 @@ void thread_resched(void) {
     thread_t *current_thread = get_current_thread();
     uint cpu = arch_curr_cpu_num();
 
+    //dprintf(INFO, "thread_resched called on thread %p(%s) on core %d\n", current_thread, current_thread->name, cpu);
+
     DEBUG_ASSERT(arch_ints_disabled());
     DEBUG_ASSERT(spin_lock_held(&thread_lock));
     DEBUG_ASSERT(current_thread->state != THREAD_RUNNING);
@@ -601,6 +603,8 @@ void thread_yield(void) {
 
     THREAD_STATS_INC(yields);
 
+    dprintf(INFO, "thread_yield\n");
+
     /* we are yielding the cpu, so stick ourselves into the tail of the run queue and reschedule */
     current_thread->state = THREAD_READY;
     current_thread->remaining_quantum = 0;

platform/bcm28xx/platform.c

@@ -208,6 +208,10 @@ void platform_early_init(void) {
 }
 
 void platform_init(void) {
+  uint32_t r28, sp;
+  __asm__ volatile ("mov %0, r28" : "=r"(r28));
+  __asm__ volatile ("mov %0, sp" : "=r"(sp));
+  dprintf(INFO, "platform_init\nr28: 0x%x\nsp: 0x%x\n", r28, sp);
     uart_init();
 #if BCM2837
     init_framebuffer();

todo.txt

@@ -0,0 +1,4 @@
+use TARGET_HAS_DEBUG_LED on rpi
+
+fix \r\n issues
+an IRQ between \r and \n can lead to text getting overwritten