Name		Name	Last commit message	Last commit date
Latest commit History 133 Commits
innovation_project-master		innovation_project-master
innovation_project-master1		innovation_project-master1
resources		resources
simulation-only		simulation-only
synthesis		synthesis
C:\Users\jsbosset\Desktop		C:\Users\jsbosset\Desktop
KROS.v		KROS.v
KROS.v.bak		KROS.v.bak
KROS_simonly.v		KROS_simonly.v
RAM2Port.v		RAM2Port.v
RAM2Port_bb.v		RAM2Port_bb.v
RAM2Port_inst.v		RAM2Port_inst.v
README.md		README.md
ROM2Port.v		ROM2Port.v
ROM2Port_bb.v		ROM2Port_bb.v
ROM2Port_inst.v		ROM2Port_inst.v
ROM_state.v		ROM_state.v
ROM_state.v.bak		ROM_state.v.bak
ROM_state_loop.v		ROM_state_loop.v
State_Machine_run_msim_rtl_verilog.do		State_Machine_run_msim_rtl_verilog.do
bcd_conv.v		bcd_conv.v
bcd_conv.v.bak		bcd_conv.v.bak
clk_div.v		clk_div.v
debouncer.v		debouncer.v
debouncer.v.bak		debouncer.v.bak
mif_gen.mif		mif_gen.mif
mif_gen.ver		mif_gen.ver
modelsim.ini		modelsim.ini
seg_disp.v		seg_disp.v
seg_disp.v.bak		seg_disp.v.bak
sequencer.v		sequencer.v
sequencer.v.bak		sequencer.v.bak
stateMachine_taglistRAM.v		stateMachine_taglistRAM.v
state_machine_do.do		state_machine_do.do
taglist_sm_verilog.do		taglist_sm_verilog.do
taglist_state_machine_run_msim_rtl_verilog.do		taglist_state_machine_run_msim_rtl_verilog.do
tb_kros.v		tb_kros.v
tb_state_ROM.v		tb_state_ROM.v
tb_state_ROM_loop.v		tb_state_ROM_loop.v
tb_taglist_RAM.v		tb_taglist_RAM.v
tb_throttle.v		tb_throttle.v
throttle.v		throttle.v
throttle.v.bak		throttle.v.bak
wavehh.do		wavehh.do
wavell.do		wavell.do

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innovation_project

Knight Rider on Steroids. Jake was here