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Replace R_LARCH_SOP_PUSH_* with regular bit extraction relocation types #9

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MaskRay opened this issue Aug 24, 2021 · 1 comment
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@MaskRay
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MaskRay commented Aug 24, 2021

Per @xen0n on #3 (comment)

Plus it seems there's a stack machine implemented with relocation records. I think this is bad for these reasons:

Fragility could ensue due to tools not respecting relative order of relocation records on the same address;
It's superficial, conveying actions and not motivations, which is generally bad smell in software engineering;
Not much complexity is shed by the introduction of intended flexibility here, so it wasn't exactly profitable either;
No prior cases wheresoever found in public code, so it's not sure if the scheme is to be appreciated universally.
I suggest removing these if possible; at the very least, continue to support this model if you MUST support the already existing early LA world with the upstreamed toolchains, but stop generating these in the future; define distinct relocation types for all the macros utilizing computation in their expansions, just like any other architecture.

As a replacement, some new relocation types with fixed bit extraction and shift can be used.

  • The stack machine requires considerable complexity in the assembler. Assemblers use sym_a-sym-b+const to represent a value. It is difficult to represent shifts on a symbolic operand.
  • The stack operating relocations waste space in relocatable object files.
  • The stack machine is not clear what parallel relocation resolving should do.
  • Various assembly producers need to deal with the complexity of a plethora of stack operating relocations.
xry111 added a commit to xry111/llvm-project that referenced this issue Apr 20, 2022
This fixes rustc code generation for "reltable" entries, like:

    i32 trunc (
        i64 sub (
	    i64 ptrtoint (<{ [1 x i8] }>* @alloc47 to i64),
	    i64 ptrtoint ([5 x i32]* @reltable.func to i64)
	) to i32
    )

We need either an ADD32/SUB32 pair or a PUSH_PCREL/POP pair, so currently
we don't have any better solution for this.  RISC-V uses a single PCREL
reloc for this OTOH.
See loongson/LoongArch-Documentation#9.
@ChenghuaXu
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Hi, The new reloc type #57 has been merged, Plz close this.

@MaskRay MaskRay closed this as completed Dec 14, 2022
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