Skip to content

Commit

Permalink
Override spike from upstream package, change output to spike
Browse files Browse the repository at this point in the history
  • Loading branch information
hcallahan-lowrisc committed Jan 23, 2024
1 parent b140867 commit dc0e00b
Show file tree
Hide file tree
Showing 3 changed files with 17 additions and 29 deletions.
2 changes: 1 addition & 1 deletion pkgs/default.nix
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@
python_ot = pkgs.callPackage ./python_ot {inherit inputs;};
bazel_ot = pkgs.callPackage ./bazel_ot {};
llvm_cheriot = pkgs.callPackage ./llvm_cheriot.nix {};
ibex-cosim = pkgs.callPackage ./ibex-cosim.nix {};
spike_ibex_cosim = pkgs.callPackage ./spike.nix {};
}
// pkgs.lib.optionalAttrs (pkgs.system == "x86_64-linux") {
lowrisc-toolchain-gcc-rv32imcb = pkgs.callPackage ./lowrisc-toolchain-gcc-rv32imcb.nix {};
Expand Down
28 changes: 0 additions & 28 deletions pkgs/ibex-cosim.nix

This file was deleted.

16 changes: 16 additions & 0 deletions pkgs/spike.nix
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
{
fetchFromGitHub,
spike,
}:
# The lowRISC Ibex processor (https://github.com/lowRISC/ibex) uses a fork of
# spike as an Instruction Set Simulator (ISS) for a cosimulation testbench in
# its Design Verification (DV) environment.
spike.overrideAttrs (_: prev: {
src = fetchFromGitHub {
owner = "lowRISC";
repo = "riscv-isa-sim";
rev = "ibex-cosim-v0.5";
sha256 = "sha256-LK/IXmRHrGxaMRudcUYmeZV5eXU8eH7ruIw7kliumdY=";
};
configureFlags = (prev.configureFlags or []) ++ ["--enable-commitlog" "--enable-misaligned"];
})

0 comments on commit dc0e00b

Please sign in to comment.