Update lowrisc_ibex to lowRISC/cheriot-ibex@279ec8d5

Update code from upstream repository https://github.com/lowrisc/cheriot-ibex.git to revision 279ec8d5d6f677c8c71a462291ea17d6cbb8eeab * Feed RV32M through ibexc_top_tracing/ibexc_top (Greg Chadwick) * Switch to no bitmanip by default (Greg Chadwick) * RV32B parameter now passed in ibexc_top (Marno van der Maas) * PVIO needs 3 bit indexes not 4 (Marno van der Maas) * cheri_ex_err_info flop signals weren't used (Marno van der Maas) * Add UNOPTFLAT waiver to ibex_id_stage (Adrian Lees) * Patched prim_arbiter.vlt file (Adrian Lees) * Patch to add UNOPTFLAT waiver to prim_arbiter_ppc (Adrian Lees) * [rtl] Add defaults to some paramaters (Greg Chadwick) * [rtl] Fix ICache scramble key valid input (Greg Chadwick) * [rtl] Remove stray comma (Greg Chadwick) * [rtl] Enable use of ICache with ibexc_top (Greg Chadwick) * [util] Update check_tool_requirements.py (Gary Guo) * Update lowrisc_ip to lowRISC/opentitan@f235838a9e (Marno van der Maas) * Added patch to remove alert prim from all group (Marno van der Maas) * [vendor] Patch updated based on OpenTitan/36a2d3c (Marno van der Maas) * [dv] Alter cov_merge.tcl patch so icache coverage collection works (Greg Chadwick) * Add patch for lowrisc_ip (Harry Callahan) * [vendor] Update patch file based on upstream OpenTitan (Marno van der Maas) * Feed CHERI errors out to top module (Marno van der Maas) Signed-off-by: Marno van der Maas <[email protected]>
lowRISC · Jan 15, 2025 · 32d91ce · 32d91ce
1 parent cc78ef2
commit 32d91ce
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Showing 4 changed files with 9 additions and 5 deletions.
diff --git a/vendor/lowrisc_ibex.lock.hjson b/vendor/lowrisc_ibex.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowrisc/cheriot-ibex.git
-    rev: adc4803d5d13cdf5a629b3f53fb4ce8d1ac38fe5
+    rev: 279ec8d5d6f677c8c71a462291ea17d6cbb8eeab
   }
 }
diff --git a/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv b/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
@@ -1015,7 +1015,8 @@ module ibex_cs_registers import cheri_pkg::*;  #(
     .rd_error_o()
   );
 
-  logic  cheri_exception_code = mcause_q == 6'h1C;
+  logic  cheri_exception_code;
+  assign cheri_exception_code = mcause_q == 6'h1C;
   // Bounds violation
   assign cheri_err_o[0] = cheri_exception_code ? (mtval_q[4:0] == 5'h01) : 1'b0;
   // Tag violation

diff --git a/vendor/lowrisc_ibex/rtl/ibexc_top.sv b/vendor/lowrisc_ibex/rtl/ibexc_top.sv
@@ -26,6 +26,7 @@ module ibexc_top import ibex_pkg::*; import cheri_pkg::*; #(
   parameter int unsigned MHPMCounterNum   = 0,
   parameter int unsigned MHPMCounterWidth = 40,
   parameter bit          RV32E            = 1'b0,
+  parameter rv32m_e      RV32M            = RV32MFast,
   parameter rv32b_e      RV32B            = RV32BNone,
   parameter bit          WritebackStage   = 1'b1,
   parameter bit          BranchPredictor  = 1'b0,
@@ -258,8 +259,8 @@ module ibexc_top import ibex_pkg::*; import cheri_pkg::*; #(
     .MHPMCounterNum   (MHPMCounterNum  ),
     .MHPMCounterWidth (MHPMCounterWidth),
     .RV32E            (RV32E),
-    .RV32M            (RV32MFast),
-    .RV32B            (RV32BNone),
+    .RV32M            (RV32M),
+    .RV32B            (RV32B),
     .BranchTargetALU  (1'b1),
     .ICache           (ICache),
     .ICacheECC        (1'b0),

diff --git a/vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv b/vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv
@@ -14,12 +14,13 @@ module ibexc_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
   parameter int unsigned DmHaltAddr       = 32'h1A110800,
   parameter int unsigned DmExceptionAddr  = 32'h1A110808,
   parameter bit          RV32E            = 1'b0,
+  parameter rv32m_e      RV32M            = RV32MFast,
+  parameter rv32b_e      RV32B            = RV32BNone,
   parameter bit          CheriTBRE        = 1'b1,
   parameter bit          CheriStkZ        = 1'b1,
   parameter bit          DbgTriggerEn     = 1'b1,
   parameter int unsigned DbgHwBreakNum    = 4,
   parameter int unsigned MHPMCounterNum   = 0,
-  parameter rv32b_e      RV32B            = RV32BFull,
   parameter int unsigned HeapBase         = 32'h2001_0000,
   parameter int unsigned TSMapBase        = 32'h2004_0000, // 4kB default
   parameter int unsigned TSMapSize        = 1024,          // in words
@@ -155,6 +156,7 @@ module ibexc_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
     .DbgTriggerEn     (DbgTriggerEn),
     .DbgHwBreakNum    (DbgHwBreakNum),
     .RV32E            (RV32E),
+    .RV32M            (RV32M),
     .RV32B            (RV32B),
     .WritebackStage   (1'b1),
     .BranchPredictor  (1'b0),