Restore prim_flop_2sync timing exceptions

It appears the `ASYNC_REG` property does not infer timing exceptions.
It seem we're lucky at 40 MHz clk_sys that it is possible to meet timing
without them, but better to make timing easier where possible.
Restore the previous `set_false_path` commands for `prim_flop_2sync`.

data/pins_sonata.xdc

@@ -344,8 +344,8 @@ set_property DONT_TOUCH TRUE [get_cells -hier -filter {ORIG_REF_NAME == prim_flo
 set_property DONT_TOUCH TRUE [get_cells -hier -filter {ORIG_REF_NAME == prim_fifo_async}]
 set_property DONT_TOUCH TRUE [get_cells -hier -filter {ORIG_REF_NAME == prim_fifo_async_simple}]
 # Set ASYNC_REG on the flops our flop-based CDC synchronisers to get
-# special place&route to reduce the MTBF from metastability, to prevent
-# dangerous optimisations, and to infer D-pin timing exceptions.
+# special place&route to reduce the MTBF from metastability, and to prevent
+# dangerous optimisations. Note, this appears NOT to include timing exceptions.
 # See the ASYNC_REG sections of UG901 or UG912 for details.
 set sync_cells [get_cells -hier -filter {ORIG_REF_NAME == prim_flop_2sync}]
 set sync_clk_in [get_pins -of $sync_cells -filter {REF_PIN_NAME == clk_i}]

data/synth_timing.xdc

@@ -793,8 +793,16 @@ set_false_path -setup -from [get_ports {pmod0[2] pmod1[2]}] -to [get_clocks vclk
 set_false_path -hold -from [get_clocks vclk_sys] -to [get_ports {pmod0[1] pmod1[1]}]
 
 ## prim_flop_2sync
-# Explicit false_path not needed so long as ASYNC_REG property is correctly
-# set on the underlying flops earlier in the flow.
+# Set false_path timing exceptions on 2-stage synchroniser inputs.
+# Target the inputs because the flops inside are clocked by the destination.
+#
+# Reliant on the hierarchical pin names of the synchronisers remaining
+# unchanged during synthesis due to use of DONT_TOUCH or KEEP_HIERARCHY.
+set sync_cells [get_cells -hier -filter {ORIG_REF_NAME == prim_flop_2sync}]
+set sync_pins [get_pins -filter {REF_PIN_NAME =~ d_i*} -of $sync_cells]
+# Filter out any that do not have a real timing path (fail to find leaf cell).
+set sync_endpoints [filter [all_fanout -endpoints_only -flat $sync_pins] IS_LEAF]
+set_false_path -to $sync_endpoints
 
 ## prim_fifo_async and prim_fifo_async_simple
 # Set false_path timing exceptions on asynchronous fifo outputs.