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Update lowrisc_ibex to lowRISC/cheriot-ibex@8474cf81
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Update code from upstream repository
https://github.com/lowrisc/cheriot-ibex.git to revision
8474cf81d0f06fd727d8e66bc356fa18822bbf8d

Signed-off-by: Marno van der Maas <[email protected]>
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@marnovandermaas @HU90m
marnovandermaas authored and HU90m committed Mar 25, 2024
1 parent 219a61c commit f8b2547
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Showing 29 changed files with 1,456 additions and 185 deletions.
2 changes: 1 addition & 1 deletion vendor/lowrisc_ibex.lock.hjson
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Expand Up @@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowrisc/cheriot-ibex.git
rev: 22327690d525cc59baf56d32b4856307664039cb
rev: 8474cf81d0f06fd727d8e66bc356fa18822bbf8d
}
}
2 changes: 1 addition & 1 deletion vendor/lowrisc_ibex/README.md
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Expand Up @@ -88,7 +88,7 @@ Note that the main CPU pipeline, TBRE and STKZ all use the load-store unit to ac

## Backward compatibility

cheriot-ibex provides a backward-compatibility mode which is enabled by setting the input cheri_pmode_i = 1. In this mode, all CheirIoT features are disabled. The cheriot-ibex core is logically equivalent to the non-CHERIoT ibex core and runs unmodified RV32IMC binaries.
cheriot-ibex provides a backward-compatibility mode which is enabled by setting the input cheri_pmode_i = 0. In this mode, all CHERIoT features are disabled. The cheriot-ibex core is logically equivalent to the non-CHERIoT ibex core and runs unmodified RV32IMC binaries.

## Design configuration parameters

Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ibex/dv/cheriot/tb/cap_err_gen.sv
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Expand Up @@ -140,7 +140,7 @@ module cap_err_gen import ibex_pkg::*; import cheri_pkg::*; (

assign is_rv32_lsu = dut.u_ibex_top.u_ibex_core.g_cheri_ex.u_cheri_ex.rv32_lsu_req_i;
assign is_cheri_lsu = cheri_exec_id & (cheri_operator[CLOAD_CAP] | cheri_operator[CSTORE_CAP]);
assign pc_in_isr = (pc_id >= 32'h8000_0000) & (pc_id < 32'h8000_0200);
assign pc_in_isr = dut.u_ibex_top.u_ibex_core.id_stage_i.controller_i.controller_dv_ext_i.cpu_in_isr;

assign err_failed = err_active & dut.u_ibex_top.u_ibex_core.g_cheri_ex.u_cheri_ex.lsu_req_o &
(~dut.u_ibex_top.u_ibex_core.g_cheri_ex.u_cheri_ex.lsu_cheri_err_o) &
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34 changes: 34 additions & 0 deletions vendor/lowrisc_ibex/dv/cheriot/tb/cheriot_dv_pkg.sv
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@@ -0,0 +1,34 @@
// Copyright Microsoft Corporation
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

package cheriot_dv_pkg;
import cheri_pkg::*;

parameter logic [31:0] DRAMStartAddr = 32'h8000_0000;
parameter logic [31:0] TsMapStartAddr = 32'h8300_0000;

typedef struct packed {
logic [7:0] flag;
logic is_cap;
logic we;
logic [3:0] be;
logic [29:0] addr32;
logic [32:0] wdata;
logic [32:0] rdata;
logic err;
} mem_cmd_t;

typedef struct packed {
logic is_cap;
logic we;
logic [1:0] rv32_type;
logic [31:0] addr;
reg_cap_t wcap;
logic [31:0] wdata;
reg_cap_t rcap;
logic [31:0] rdata;
logic err;
} lsu_cmd_t;

endpackage
44 changes: 24 additions & 20 deletions vendor/lowrisc_ibex/dv/cheriot/tb/core_ibex_fcov_if.sv
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Expand Up @@ -695,27 +695,26 @@ interface core_ibex_fcov_if import ibex_pkg::*; import cheri_pkg::*; (
// New coverage points
//

// ignore_bins ignore = {[16:31]}; // RV32E/CHERIoT, 16 regs only
cp_rs1_addr: coverpoint id_stage_i.rf_raddr_a_o[3:0] iff (id_stage_i.rf_ren_a) {
bins bin0 = {0};
bins bin1to7 = {[1:7]};
bins bin8to14 = {[8:14]};
bins bin15 = {15};
cp_rs1_addr: coverpoint id_stage_i.rf_raddr_a_o[4:0] iff (id_stage_i.rf_ren_a) {
bins bin0 = {0};
bins bin1to14 = {[1:14]};
bins bin15 = {15};
bins bin16to31 = {[16:31]}; // for CHERIoT negative case
}

cp_rs2_addr: coverpoint id_stage_i.rf_raddr_b_o[3:0] iff (id_stage_i.rf_ren_b) {
bins bin0 = {0};
bins bin1to7 = {[1:7]};
bins bin8to14 = {[8:14]};
bins bin15 = {15};
cp_rs2_addr: coverpoint id_stage_i.rf_raddr_b_o[4:0] iff (id_stage_i.rf_ren_b) {
bins bin0 = {0};
bins bin1to14 = {[1:14]};
bins bin15 = {15};
bins bin16to31 = {[16:31]}; // for CHERIoT negative case
}

cp_rd_addr: coverpoint id_stage_i.rf_waddr_id_o[3:0] iff
cp_rd_addr: coverpoint id_stage_i.rf_waddr_id_o[4:0] iff
(id_stage_i.rf_we_id_o | g_cheri_ex.u_cheri_ex.cheri_rf_we_o) {
bins bin0 = {0};
bins bin1to7 = {[1:7]};
bins bin8to14 = {[8:14]};
bins bin15 = {15};
bins bin0 = {0};
bins bin1to14 = {[1:14]};
bins bin15 = {15};
bins bin16to31 = {[16:31]}; // for CHERIoT negative case
}

// all CHERIoT instructions enumerated
Expand Down Expand Up @@ -763,7 +762,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; import cheri_pkg::*; (
// bins bin2 = {4'b0011}; // base_cor = 0, top_cor = -1, impossible case
bins bin3 = {4'b1100};
// bins bin4 = {4'b1101}; // impossible case
// bins bin5 = {4'b1111}; // impossible case
bins bin5 = {4'b1111};
illegal_bins illegal = default;
}

Expand Down Expand Up @@ -822,7 +821,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; import cheri_pkg::*; (
// bins bin2 = {4'b0011};
bins bin3 = {4'b1100};
// bins bin4 = {4'b1101};
// bins bin5 = {4'b1111};
bins bin5 = {4'b1111};
illegal_bins illegal = default;
}

Expand Down Expand Up @@ -942,7 +941,9 @@ interface core_ibex_fcov_if import ibex_pkg::*; import cheri_pkg::*; (
cp_trvk_cond: coverpoint {g_trvk_stage.cheri_trvk_stage_i.trvk_status,
g_trvk_stage.cheri_trvk_stage_i.cap_good_q[2],
g_trvk_stage.cheri_trvk_stage_i.range_ok_q[2]} iff
(g_trvk_stage.cheri_trvk_stage_i.rf_trvk_en_o);
(g_trvk_stage.cheri_trvk_stage_i.rf_trvk_en_o) {
wildcard ignore_bins ignore = {3'b?0?}; // if cap is not good, revocaton status/rang_ok are don't cares
}

cp_trvk_stall: coverpoint id_stage_i.stall_cheri_trvk;

Expand Down Expand Up @@ -990,6 +991,8 @@ interface core_ibex_fcov_if import ibex_pkg::*; import cheri_pkg::*; (
cheri_tbre_wrapper_i.g_tbre.cheri_tbre_i.tbre_lsu_req_o,
cheri_tbre_wrapper_i.g_stkz.cheri_stkz_i.stkz_lsu_req_o};

cp_tbrewrp_blk1_cancel: coverpoint cheri_tbre_wrapper_i.tbre_wrapper_dv_ext_i.fcov_blk1_cancel;

cp_stkz_sm: coverpoint cheri_tbre_wrapper_i.g_stkz.cheri_stkz_i.stkz_fsm_q {
bins good[] = {[0:2]};
illegal_bins bad = default;
Expand Down Expand Up @@ -1092,7 +1095,8 @@ interface core_ibex_fcov_if import ibex_pkg::*; import cheri_pkg::*; (

// exception_stall_instr_cross: cross cp_ls_pmp_exception, cp_ls_error_exception, cp_ls_cheri_exception,
exception_stall_instr_cross: cross cp_ls_exception,
cp_id_instr_category, cp_stall_type_id, instr_unstalled, cp_irq_pending, cp_debug_req {
// cp_id_instr_category, cp_stall_type_id, instr_unstalled, cp_irq_pending, cp_debug_req { // QQQ add cp_debug_req back later
cp_id_instr_category, cp_stall_type_id, instr_unstalled, cp_irq_pending {
illegal_bins illegal =
// Only Div, Mul, Branch and Jump instructions can see an instruction stall
(!binsof(cp_id_instr_category) intersect {InstrCategoryDiv, InstrCategoryMul,
Expand Down
67 changes: 44 additions & 23 deletions vendor/lowrisc_ibex/dv/cheriot/tb/data_mem_model.sv
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Expand Up @@ -5,7 +5,7 @@
//
// data interface/memory model
//
module data_mem_model (
module data_mem_model import cheriot_dv_pkg::*; (
input logic clk,
input logic rst_n,

Expand All @@ -14,17 +14,21 @@ module data_mem_model (
input logic [3:0] RESP_WMAX,

input logic err_enable,
input logic ignore_stkz,

input logic data_req,
input logic data_we,
input logic [3:0] data_be,
input logic data_is_cap,
input logic [31:0] data_addr,
input logic [32:0] data_wdata,
input logic [7:0] data_flag,

output logic data_gnt,
output logic data_rvalid,
output logic [32:0] data_rdata,
output logic data_err,
output mem_cmd_t data_resp_info,

input logic tsmap_cs,
input logic [15:0] tsmap_addr,
Expand All @@ -34,7 +38,8 @@ module data_mem_model (
input logic [63:0] mmreg_coreout,

output logic [3:0] err_enable_vec,
output logic [2:0] intr_ack
output logic [2:0] intr_ack,
output logic uart_stop_sim
);

localparam int unsigned DRAM_AW = 16;
Expand Down Expand Up @@ -71,51 +76,45 @@ module data_mem_model (
logic mmreg_sel, mmreg_cs;
logic [7:0] mmreg_addr32;

logic data_req_isr;
logic mem_req_isr;
logic [7:0] mem_flag;

mem_obi_if #(
.DW (33)
) u_mem_obj_if (
.clk (clk),
.rst_n (rst_n),
.clk_i (clk),
.rst_ni (rst_n),
.GNT_WMAX (GNT_WMAX),
.RESP_WMAX (RESP_WMAX),
.data_req (data_req),
.data_req_isr (data_req_isr),
.data_we (data_we),
.data_be (data_be),
.data_is_cap (data_is_cap),
.data_addr (data_addr),
.data_wdata (data_wdata),
.data_flag (data_flag),
.data_gnt (data_gnt),
.data_rvalid (data_rvalid),
.data_rdata (data_rdata),
.data_err (data_err),
.data_resp_info (data_resp_info),
.mem_cs (mem_cs),
.mem_we (mem_we),
.mem_be (mem_be),
.mem_req_isr (mem_req_isr),
.mem_flag (mem_flag),
.mem_addr32 (mem_addr32),
.mem_wdata (mem_wdata),
.mem_rdata (mem_rdata),
.mem_err (mem_err)
);

//
// Tracking CPU execution of startup/exception handler and
// suppress error injection during the phase
//

assign data_req_isr = dut.u_ibex_top.u_ibex_core.id_stage_i.instr_executing &
dut.u_ibex_top.u_ibex_core.load_store_unit_i.lsu_req_i &
~dut.u_ibex_top.u_ibex_core.load_store_unit_i.cur_req_is_tbre &
(dut.u_ibex_top.u_ibex_core.id_stage_i.pc_id_i >= 32'h8000_0000) &
(dut.u_ibex_top.u_ibex_core.id_stage_i.pc_id_i < 32'h8000_0200);
//
// memory signals (sampled @posedge clk)
//
logic dram_sel_q, tsram_p0_sel_q, mmreg_sel_q;
logic mem_req_isr, mem_req_stkz;

assign mem_req_stkz = mem_flag[2];
assign mem_req_isr = mem_flag[0];
assign mem_rdata = dram_sel_q ? dram_rdata : (tsram_p0_sel_q ? {1'b0, tsram_p0_rdata} :
(mmreg_sel_q ? {1'b0, mmreg_rdata} : 33'h0));
// mem_err is in themem_cs
Expand All @@ -125,9 +124,12 @@ module data_mem_model (
// DRAM (data RAM)
// starting at 0x8000_0000
//
// don't generate memory access if
// - responds with an error, or
// - accesses from stkz is supposed to be ignored.
assign dram_addr32 = mem_addr32[DRAM_AW-1:0];
assign dram_sel = mem_cs & mem_addr32[29] & (mem_addr32[28:DRAM_AW+2] == 0);
assign dram_cs = dram_sel & ~mem_err;
assign dram_cs = dram_sel & ~mem_err & (~mem_req_stkz | ~ignore_stkz);

always @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
Expand Down Expand Up @@ -169,8 +171,10 @@ module data_mem_model (
if (~rst_n) begin
dram_err_schd <= 1'b0;
end else begin
if (dram_sel)
dram_err_schd <= err_enable & ((ERR_RATE == 0) ? 1'b0 : ($urandom()%(2**(8-ERR_RATE))==0));
if (~err_enable)
dram_err_schd <= 1'b0;
else if (dram_sel)
dram_err_schd <= (ERR_RATE == 0) ? 1'b0 : ($urandom()%(2**(8-ERR_RATE))==0);
end
end
//
Expand Down Expand Up @@ -214,8 +218,10 @@ module data_mem_model (
if (~rst_n) begin
tsram_p0_err_schd <= 1'b0;
end else begin
if (tsram_p0_sel)
tsram_p0_err_schd <= err_enable & ((ERR_RATE == 0) ? 1'b0 : ($urandom()%(2**(8-ERR_RATE))==0));
if (~err_enable)
tsram_p0_err_schd <= 1'b0;
else if (tsram_p0_sel)
tsram_p0_err_schd <= (ERR_RATE == 0) ? 1'b0 : ($urandom()%(2**(8-ERR_RATE))==0);
end
end

Expand Down Expand Up @@ -310,4 +316,19 @@ module data_mem_model (
end
end

// UART printout
initial begin
uart_stop_sim = 1'b0;
@(posedge rst_n);

while (1) begin
@(posedge clk);
if (mmreg_cs && mem_we && (mmreg_addr32 == 'h80)) // 0x8380_0200
if (mem_wdata[7])
uart_stop_sim = 1'b1;
else
$write("%c", mem_wdata[7:0]);
end
end

endmodule
4 changes: 2 additions & 2 deletions vendor/lowrisc_ibex/dv/cheriot/tb/dii_if.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@

module dii_if (
input logic clk_i,
input logic rstn_i,
input logic rst_ni,

// DII generator interface
input logic [31:0] dii_insn_0_i,
Expand Down Expand Up @@ -65,7 +65,7 @@ module dii_if (
int flush_cnt;
logic flush_active;

@(posedge rstn_i);
@(posedge rst_ni);
hqueue = {};

while (1) begin
Expand Down
14 changes: 10 additions & 4 deletions vendor/lowrisc_ibex/dv/cheriot/tb/instr_mem_model.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -39,22 +39,26 @@ module instr_mem_model (
mem_obi_if #(
.DW (32)
) u_mem_obj_if (
.clk (clk),
.rst_n (rst_n),
.clk_i (clk),
.rst_ni (rst_n),
.GNT_WMAX (GNT_WMAX),
.RESP_WMAX (RESP_WMAX),
.data_req (instr_req),
.data_we (1'b0),
.data_be (4'hf),
.data_is_cap (1'b0),
.data_addr (instr_addr),
.data_wdata (32'h0),
.data_flag (8'h0),
.data_gnt (instr_gnt),
.data_rvalid (instr_rvalid),
.data_rdata (instr_rdata),
.data_err (instr_err),
.data_resp_info (),
.mem_cs (mem_cs),
.mem_we (),
.mem_be (),
.mem_flag (),
.mem_addr32 (mem_addr32),
.mem_wdata (),
.mem_rdata (mem_rdata),
Expand Down Expand Up @@ -83,8 +87,10 @@ module instr_mem_model (
if (~rst_n) begin
iram_err_q <= 1'b0;
end else begin
if (mem_cs)
iram_err_q <= err_enable & ((ERR_RATE == 0) ? 1'b0 : ($urandom()%(2**(8-ERR_RATE))==0));
if (~err_enable)
iram_err_q <= 1'b0;
else if (mem_cs)
iram_err_q <= (ERR_RATE == 0) ? 1'b0 : ($urandom()%(2**(8-ERR_RATE))==0);

end
end
Expand Down
11 changes: 7 additions & 4 deletions vendor/lowrisc_ibex/dv/cheriot/tb/intr_gen.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,8 @@ module intr_gen (

logic [2:0] irq;

assign irq_o = intr_en & irq; // hard gate irq output (otherwise nwait cause delay)
//assign irq_o = intr_en & irq; // hard gate irq output (otherwise nwait cause delay)
assign irq_o = irq;

initial begin
int nwait;
Expand All @@ -35,9 +36,11 @@ module intr_gen (
if (intr_en && (INTR_INTVL != 0)) begin
nwait = ((rand32 % (2** INTR_INTVL)) + 1) * 10; // wait at least 10 clk cycles
repeat (nwait) @(posedge clk);
// irq = rand32[15:0] % 7 + 1; // new interrupt
irq = {2'b00, rand32[0]}; // just do irq_external now. irq_timer causes trouble in sail
//$display ("going irq=1 @%t", $time);
if (intr_en) begin // test intr_en again
// irq = rand32[15:0] % 7 + 1; // new interrupt
irq = {2'b00, rand32[0]}; // just do irq_external now. irq_timer causes trouble in sail
//$display ("going irq=1 @%t", $time);
end
end else begin
@(posedge clk);
end
Expand Down
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