Update lowrisc_ibex to lowrisc/cheriot-ibex@a745108a #125
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Update code from upstream repository https://github.com/lowrisc/cheriot-ibex.git to revision a745108ad9ad50de3f8420ccf3dfc5909e92cbf0 * [util] Update check_tool_requirements.py (Gary Guo) * Update lowrisc_ip to lowRISC/opentitan@f235838a9e (Marno van der Maas) * Added patch to remove alert prim from all group (Marno van der Maas) * [vendor] Patch updated based on OpenTitan/36a2d3c (Marno van der Maas) * [dv] Alter cov_merge.tcl patch so icache coverage collection works (Greg Chadwick) * Add patch for lowrisc_ip (Harry Callahan) * [vendor] Update patch file based on upstream OpenTitan (Marno van der Maas) * Feed CHERI errors out to top module (Marno van der Maas) * Remove prim alert from build (Marno van der Maas) * Fix tracing (Marno van der Maas) * Update two port RAM for Sonata (Marno van der Maas) * Patch reading memory files taken from upstream (Marno van der Maas) * Various Verilator lint patches (Marno van der Maas) * Use ibexc_top since that is used in SAFE (Marno van der Maas) * Add FPGA primitives (Marno van der Maas) * fixed cheri_csr_always_ok (missing h counters) in ibex_decoder (Kunyan Liu) * updated functional coverage, minor RTL cleanup (rf_we) (Kunyan Liu) * updated dv/cheriot/tests for the new forward/backward sentry types (Kunyan Liu) * added support for the new forward/backward sentry types (Kunyan Liu) * more exception-related assertion fixes in ibex_controller (Kunyan Liu) * fixed IbexDontSkipExceptionReq assertion in controller (Kunyan Liu) * added illegal_regs_cheri to decoder (generate exceptions for regaddr > 15) (Kunyan Liu) * added handling for pc wraparound case in if_stage (issue lowrisc/cheriot-ibex#34) (Kunyan Liu) * added coremark test (Kunyan Liu) * checking in sanity tests (Kunyan Liu) * Update README.md (Kunyan Liu) * fixed illegal instruction warning in controller (Kunyan Liu) * added CSR cheri safe-list (no ASR) access feature (Kunyan Liu) * removed speculative fetching for cjal/cjalr, rvfi and assertion fixes (Kunyan Liu) * fixed mprv (see cheriot-ibex issue lowrisc/cheriot-ibex#35) and data-dependent behavior in fetch_fifo (potential side-channel leakage (Kunyan Liu) * fixed FV issues (pcc2mepcc, csr/mret ASR permission fault, etc) (Kunyan Liu) * updated core_ibex_fcov (added csethigh) (Kunyan Liu) * Ignore build directory (Marno van der Maas) * Fix reference to rst_ni in tb code (Marno van der Maas) * Fix assignments in memory model (Marno van der Maas) * Add missing files for Verlator build (Marno van der Maas) * Add flags for Verilator version 5 (Marno van der Maas) * fixed mtcc/mepcc legalization to match sail (Kunyan Liu) * fixed more exception handling priority issues (Kunyan Liu) * checked in more dv/cheriot files (Kunyan Liu) * added csethigh insn and updated test case (Kunyan Liu) Signed-off-by: Marno van der Maas <[email protected]>
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Simulation is building via FuseSoC but not via Nix. It is hitting and "UNOPTFLAT" warning which should be waived via this line: Anyone know why Nix is failing to pick up this waiver? |
Nix builds via FuseSoC as well. It's likely an environment problem. What version of Verilator are you using? (We are currently on version 5.022 in Sonata: #102) |
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I'm using Verilator 5.024 2024-04-05 rev v5.024 |
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Scratch this. It was because I had a |
These warnings are due to changes in CHERIoT Ibex.
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This pulls in the latest changes from upstream up to: https://github.com/microsoft/cheriot-ibex/tree/8fe0ec632dbb1f231f2c15b3d05008b55af46b37
I've run all the current test on FPGA and it seems to work fine. It also still compiles for simulation and the UART check works.