HyperRAM permanently enabled

data/xbar_main.hjson

@@ -38,7 +38,7 @@
       xbar:  false,
       addr_range: [{
         base_addr: "0x00100000",
-        size_byte: "0x00040000",
+        size_byte: "0x00020000",
       }],
     },
     { name:  "hyperram", // HyperRAM memory
@@ -58,7 +58,7 @@
       xbar:  false,
       addr_range: [{
         base_addr: "0x30000000",
-        size_byte: "0x00004000",
+        size_byte: "0x00000800",
       }],
     },
     { name:  "gpio", // General purpose input and output

dv/verilator/sonata_system_main.cc

@@ -8,7 +8,7 @@ int main(int argc, char **argv) {
   SonataSystem sonata_system(
       "TOP.top_verilator.u_sonata_system.u_sram_top.u_ram.gen_generic.u_impl_generic",
       32 * 1024, // 32k words = 128 KiB
-      "TOP.top_verilator.u_sonata_system.g_hyperram.u_hyperram.u_hyperram_model.u_ram.gen_generic.u_impl_generic",
+      "TOP.top_verilator.u_sonata_system.u_hyperram.u_hyperram_model.u_ram.gen_generic.u_impl_generic",
       256 * 1024 // 256k words = 1 MiB
   );
 

dv/verilator/sonata_verilator_lint.vlt

@@ -30,9 +30,6 @@ lint_off -rule UNOPTFLAT -file "*tlul_adapter_sram.sv" -match "*Signal unoptimiz
 // to the error responder for the HyperRAM disabled config).
 lint_off -rule UNOPTFLAT -file "*tlul_socket_m1.sv" -match "*Signal unoptimizable: Circular combinational logic: '*.u_hyperram_tl_socket.*'"
 
-// False warning we're using 32-bit initial values for DisableHyperram parameter
-lint_off -rule WIDTHTRUNC -file "*" -match "Operator VAR 'DisableHyperram' expects 1 bits on the Initial value*"
-
 // Unimportant warning where compressed and uncompress instructions are printed in the same place.
 lint_off -rule WIDTHEXPAND -file "*ibex_controller.sv" -match "*Conditional True's VARREF 'instr_compressed_i' generates 16 bits."
 

dv/verilator/top_verilator.sv

@@ -6,12 +6,10 @@
 module top_verilator (input logic clk_i, rst_ni);
   import sonata_pkg::*;
 
-  parameter bit DisableHyperram = 1'b0;
-
   // System clock frequency.
   localparam int unsigned SysClkFreq = 40_000_000;
   // HyperRAM clock frequency.
-  localparam int unsigned HRClkFreq  = 100_000_000;
+  localparam int unsigned HyperRAMClkFreq  = 100_000_000;
   localparam int unsigned BaudRate   = 921_600;
   // Number of CHERI error LEDs.
   localparam int unsigned CheriErrWidth = 9;
@@ -301,8 +299,7 @@ module top_verilator (input logic clk_i, rst_ni);
   sonata_system #(
     .CheriErrWidth   ( CheriErrWidth   ),
     .SysClkFreq      ( SysClkFreq      ),
-    .HRClkFreq       ( HRClkFreq       ),
-    .DisableHyperram ( DisableHyperram )
+    .HyperRAMClkFreq ( HyperRAMClkFreq )
   ) u_sonata_system (
     // Main system clock and reset
     .clk_sys_i      (clk_i),

rtl/fpga/clkgen_sonata.sv

@@ -4,11 +4,11 @@
 
 module clkgen_sonata  #(
   // System Clock Frequency is parameterised, allowing it to be adjusted.
-  parameter int unsigned SysClkFreq = 50_000_000,
-  parameter int unsigned HRClkFreq  = 100_000_000,
+  parameter int unsigned SysClkFreq      =  50_000_000,
+  parameter int unsigned HyperRAMClkFreq = 100_000_000,
 
   // Frequency of IO_CLK input on the FPGA board.
-  parameter int unsigned IOClkFreq = 25_000_000
+  parameter int unsigned IOClkFreq       =  25_000_000
 ) (
     // Board clock signal
     input IO_CLK,
@@ -67,15 +67,15 @@ module clkgen_sonata  #(
     .CLKOUT1_PHASE        (0.000),
     .CLKOUT1_DUTY_CYCLE   (0.500),
 
-    .CLKOUT2_DIVIDE       ((48 * IOClkFreq) / HRClkFreq),
+    .CLKOUT2_DIVIDE       ((48 * IOClkFreq) / HyperRAMClkFreq),
     .CLKOUT2_PHASE        (0.000),
     .CLKOUT2_DUTY_CYCLE   (0.500),
 
-    .CLKOUT3_DIVIDE       ((48 * IOClkFreq) / HRClkFreq),
+    .CLKOUT3_DIVIDE       ((48 * IOClkFreq) / HyperRAMClkFreq),
     .CLKOUT3_PHASE        (90.000),
     .CLKOUT3_DUTY_CYCLE   (0.500),
 
-    .CLKOUT4_DIVIDE       ((48 * IOClkFreq) / (HRClkFreq * 3)),
+    .CLKOUT4_DIVIDE       ((48 * IOClkFreq) / (HyperRAMClkFreq * 3)),
     .CLKOUT4_PHASE        (0.000),
     .CLKOUT4_DUTY_CYCLE   (0.500),
 

rtl/fpga/top_sonata.sv

@@ -202,11 +202,10 @@ module top_sonata
   import sonata_pkg::*;
 
   // System clock frequency.
-  parameter int unsigned SysClkFreq = 40_000_000;
-  parameter int unsigned HRClkFreq  = 100_000_000;
+  parameter int unsigned SysClkFreq      =  40_000_000;
+  parameter int unsigned HyperRAMClkFreq = 100_000_000;
 
   parameter SRAMInitFile    = "";
-  parameter DisableHyperram = 1'b0;
 
   // Main/board clock and reset
   logic main_clk_buf;
@@ -267,11 +266,10 @@ module top_sonata
   logic rs485_rx_enable, rs485_tx_enable;
 
   sonata_system #(
-    .CheriErrWidth   (  9             ),
-    .SRAMInitFile    ( SRAMInitFile   ),
-    .SysClkFreq      ( SysClkFreq     ),
-    .HRClkFreq       ( HRClkFreq      ),
-    .DisableHyperram ( DisableHyperram )
+    .CheriErrWidth   ( 9               ),
+    .SRAMInitFile    ( SRAMInitFile    ),
+    .SysClkFreq      ( SysClkFreq      ),
+    .HyperRAMClkFreq ( HyperRAMClkFreq )
   ) u_sonata_system (
     // Main system clock and reset
     .clk_sys_i      (clk_sys),
@@ -386,8 +384,8 @@ module top_sonata
 
   // Produce 50 MHz system clock from 25 MHz Sonata board clock.
   clkgen_sonata #(
-    .SysClkFreq(SysClkFreq),
-    .HRClkFreq (HRClkFreq)
+    .SysClkFreq      ( SysClkFreq      ),
+    .HyperRAMClkFreq ( HyperRAMClkFreq )
   ) u_clkgen(
     .IO_CLK    (mainClk),
     .IO_CLK_BUF(main_clk_buf),

rtl/ip/hyperram/rtl/hyperram.sv

@@ -8,8 +8,8 @@
 // don't want to include the full hyperram controller RTL and BFM (which in
 // particular require Xilinx encrypted IP models).
 module hyperram import tlul_pkg::*; #(
-  parameter HRClkFreq    = 100_000_000,
-  parameter HyperRAMSize = 1024 * 1024
+  parameter HyperRAMClkFreq = 100_000_000,
+  parameter HyperRAMSize    = 1024 * 1024
 ) (
   input             clk_i,
   input             rst_ni,
@@ -31,7 +31,7 @@ module hyperram import tlul_pkg::*; #(
 );
 `ifdef USE_HYPERRAM_SIM_MODEL
   localparam int SRAMModelAddrWidth = $clog2(HyperRAMSize);
-  localparam int UnusedParams = HRClkFreq + HyperRAMSize;
+  localparam int UnusedParams = HyperRAMClkFreq + HyperRAMSize;
 
   tl_h2d_t unused_tl_b;
   assign unused_tl_b = '0;
@@ -73,7 +73,7 @@ module hyperram import tlul_pkg::*; #(
 
 `else
   hbmc_tl_top #(
-    .C_HBMC_CLOCK_HZ(HRClkFreq),
+    .C_HBMC_CLOCK_HZ(HyperRAMClkFreq),
     .C_HBMC_CS_MAX_LOW_TIME_US(4),
     .C_HBMC_FIXED_LATENCY(1'B0),
     .C_IDELAYCTRL_INTEGRATED(1'B0),

rtl/system/sonata_system.sv

@@ -8,12 +8,11 @@
 module sonata_system
   import sonata_pkg::*;
 #(
-  parameter int unsigned ArdAniWidth   = 6,
-  parameter int unsigned CheriErrWidth =  9,
-  parameter SRAMInitFile               = "",
-  parameter int unsigned SysClkFreq    = 30_000_000,
-  parameter int unsigned HRClkFreq     = 100_000_000,
-  parameter bit DisableHyperram        = 1'b0
+  parameter int unsigned ArdAniWidth     = 6,
+  parameter int unsigned CheriErrWidth   =  9,
+  parameter SRAMInitFile                 = "",
+  parameter int unsigned SysClkFreq      = 30_000_000,
+  parameter int unsigned HyperRAMClkFreq = 100_000_000
 ) (
   // Main system clock and reset
   input logic                      clk_sys_i,
@@ -107,7 +106,7 @@ module sonata_system
   // Signals, types and parameters for system. //
   ///////////////////////////////////////////////
 
-  localparam int unsigned MemSize       = DisableHyperram ? 256 * 1024 : 128 * 1024; // 256 KiB
+  localparam int unsigned MemSize       = 128 * 1024; // 128 KiB
   localparam int unsigned SRAMAddrWidth = $clog2(MemSize);
   localparam int unsigned HyperRAMSize  = 1024 * 1024; // 1 MiB
   localparam int unsigned DebugStart    = 32'h1a110000;
@@ -499,54 +498,28 @@ module sonata_system
     .tl_b_o (tl_sram_b_d2h)
   );
 
-  if (DisableHyperram) begin : g_no_hyperram
-    logic unused_clk_hr;
-    logic unused_clk_hr90p;
-    logic unused_clk_hr3x;
-    logic unused_rst_hr;
-
-    assign unused_clk_hr    = clk_hr_i;
-    assign unused_clk_hr90p = clk_hr90p_i;
-    assign unused_clk_hr3x  = clk_hr3x_i;
-    assign unused_rst_hr    = rst_hr_ni;
-
-    assign hyperram_dq   = '0;
-    assign hyperram_rwds = '0;
-    assign hyperram_ckp  = 1'b0;
-    assign hyperram_ckn  = 1'b0;
-    assign hyperram_nrst = 1'b0;
-    assign hyperram_cs   = 1'b0;
-
-    tlul_err_resp u_hyperram_err (
-      .clk_i (clk_sys_i),
-      .rst_ni (rst_sys_ni),
-      .tl_h_i(tl_hyperram_ds_h2d),
-      .tl_h_o(tl_hyperram_ds_d2h)
-    );
-  end else begin : g_hyperram
-    hyperram #(
-      .HRClkFreq   (HRClkFreq),
-      .HyperRAMSize(HyperRAMSize)
-    ) u_hyperram (
-      .clk_i  (clk_sys_i),
-      .rst_ni (rst_sys_ni),
-
-      .clk_hr_i,
-      .clk_hr90p_i,
-      .clk_hr3x_i,
-      .rst_hr_ni,
-
-      .tl_i (tl_hyperram_ds_h2d),
-      .tl_o (tl_hyperram_ds_d2h),
-
-      .hyperram_dq,
-      .hyperram_rwds,
-      .hyperram_ckp,
-      .hyperram_ckn,
-      .hyperram_nrst,
-      .hyperram_cs
-    );
-  end
+  hyperram #(
+    .HyperRAMClkFreq ( HyperRAMClkFreq ),
+    .HyperRAMSize    ( HyperRAMSize    )
+  ) u_hyperram (
+    .clk_i  (clk_sys_i),
+    .rst_ni (rst_sys_ni),
+
+    .clk_hr_i,
+    .clk_hr90p_i,
+    .clk_hr3x_i,
+    .rst_hr_ni,
+
+    .tl_i (tl_hyperram_ds_h2d),
+    .tl_o (tl_hyperram_ds_d2h),
+
+    .hyperram_dq,
+    .hyperram_rwds,
+    .hyperram_ckp,
+    .hyperram_ckn,
+    .hyperram_nrst,
+    .hyperram_cs
+  );
 
   // Manual M:1 socket instantiation as xbar generator cannot deal with multiple ports for one
   // device and we want to utilize the dual port SRAM. So totally separate crossbars are generated
@@ -668,8 +641,8 @@ module sonata_system
     end
   end
 
-  // Size of revocation tag memory is 4 KiB, one bit for each 64 in SRAM
-  localparam int unsigned RevTagDepth = 4 * 1024 * 8 / BusDataWidth;
+  // Size of revocation tag memory is one bit for each 64 in SRAM.
+  localparam int unsigned RevTagDepth = (MemSize / 8) / BusDataWidth;
   localparam int unsigned RevTagAddrWidth = $clog2(RevTagDepth);
 
   tlul_adapter_sram #(

sonata.core

@@ -89,11 +89,6 @@ parameters:
     paramtype: vlogdefine
     description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
 
-  DisableHyperram:
-    datatype: bool
-    paramtype: vlogparam
-    description: Remove hyperram controller from the system (providing a larger SRAM)
-
   USE_HYPERRAM_SIM_MODEL:
     datatype: bool
     paramtype: vlogdefine
@@ -118,7 +113,6 @@ targets:
     parameters:
       - SRAMInitFile
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
-      - DisableHyperram=false
 
   sim:
     <<: *default_target
@@ -146,7 +140,6 @@ targets:
           - "--unroll-count 72"
     parameters:
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
-      - DisableHyperram=false
       - USE_HYPERRAM_SIM_MODEL=true
 
   lint:
@@ -160,7 +153,6 @@ targets:
         mode: lint-only
     parameters:
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
-      - DisableHyperram=false
       # TODO: Introduce some blackboxes for the Xilinx IP used in the hyperram
       # controller so we can lint it, for now just exclude it from the lint run.
       - USE_HYPERRAM_SIM_MODEL=true

sw/cheri/boot/boot.S

@@ -32,7 +32,7 @@ start:
 	li               a0, 0x30000000
 	csetaddr         ca0, cs0, a0
 	li               a1, 0
-	li               a2, 4096
+	li               a2, 2048
 	ccall            bl_memset
 
 	// Set cgp to correct location so globals can be used.

sw/cheri/checks/revocation_test.cc

@@ -31,7 +31,7 @@ using namespace CHERI;
   uart.address()                          = UART_ADDRESS;
   uart.bounds()                           = UART_BOUNDS;
 
-  unsigned int size_of_revocation_tags = 0x4000;  // 16 KiB
+  unsigned int size_of_revocation_tags = 0x0800;  // 2 KiB
   unsigned int number_of_words         = size_of_revocation_tags / 4;
 
   Capability<volatile uint32_t> revocation_tags = root.cast<volatile uint32_t>();

sw/cheri/common/boot.S

@@ -80,7 +80,7 @@ start:
 	li               a0, 0x30000000
 	csetaddr         ca0, cs0, a0
 	li               a1, 0
-	li               a2, 4096
+	li               a2, 2048
 	ccall            bl_memset
 
 	// Set cgp to correct location so globals can be used.