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Update lowrisc_ibex to lowrisc/cheriot-ibex@279ec8d5 #379

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Update lowrisc_ibex to lowrisc/cheriot-ibex@279ec8d5 #379

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2 changes: 1 addition & 1 deletion vendor/lowrisc_ibex.lock.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowrisc/cheriot-ibex.git
rev: adc4803d5d13cdf5a629b3f53fb4ce8d1ac38fe5
rev: 279ec8d5d6f677c8c71a462291ea17d6cbb8eeab
}
}
3 changes: 2 additions & 1 deletion vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
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Expand Up @@ -1015,7 +1015,8 @@ module ibex_cs_registers import cheri_pkg::*; #(
.rd_error_o()
);

logic cheri_exception_code = mcause_q == 6'h1C;
logic cheri_exception_code;
assign cheri_exception_code = mcause_q == 6'h1C;
// Bounds violation
assign cheri_err_o[0] = cheri_exception_code ? (mtval_q[4:0] == 5'h01) : 1'b0;
// Tag violation
Expand Down
5 changes: 3 additions & 2 deletions vendor/lowrisc_ibex/rtl/ibexc_top.sv
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Expand Up @@ -26,6 +26,7 @@ module ibexc_top import ibex_pkg::*; import cheri_pkg::*; #(
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit WritebackStage = 1'b1,
parameter bit BranchPredictor = 1'b0,
Expand Down Expand Up @@ -258,8 +259,8 @@ module ibexc_top import ibex_pkg::*; import cheri_pkg::*; #(
.MHPMCounterNum (MHPMCounterNum ),
.MHPMCounterWidth (MHPMCounterWidth),
.RV32E (RV32E),
.RV32M (RV32MFast),
.RV32B (RV32BNone),
.RV32M (RV32M),
.RV32B (RV32B),
.BranchTargetALU (1'b1),
.ICache (ICache),
.ICacheECC (1'b0),
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4 changes: 3 additions & 1 deletion vendor/lowrisc_ibex/rtl/ibexc_top_tracing.sv
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Expand Up @@ -14,12 +14,13 @@ module ibexc_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808,
parameter bit RV32E = 1'b0,
parameter rv32m_e RV32M = RV32MFast,
parameter rv32b_e RV32B = RV32BNone,
parameter bit CheriTBRE = 1'b1,
parameter bit CheriStkZ = 1'b1,
parameter bit DbgTriggerEn = 1'b1,
parameter int unsigned DbgHwBreakNum = 4,
parameter int unsigned MHPMCounterNum = 0,
parameter rv32b_e RV32B = RV32BFull,
parameter int unsigned HeapBase = 32'h2001_0000,
parameter int unsigned TSMapBase = 32'h2004_0000, // 4kB default
parameter int unsigned TSMapSize = 1024, // in words
Expand Down Expand Up @@ -155,6 +156,7 @@ module ibexc_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
.DbgTriggerEn (DbgTriggerEn),
.DbgHwBreakNum (DbgHwBreakNum),
.RV32E (RV32E),
.RV32M (RV32M),
.RV32B (RV32B),
.WritebackStage (1'b1),
.BranchPredictor (1'b0),
Expand Down
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