Backport Fix a regression

This disables a commit that improved clock accuracy but was not compatible with the PPeak+ button
makers-for-life · May 8, 2020 · 2947949 · 2947949
1 parent e13a7ef
commit 2947949
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,5 +1,10 @@
 # Changelog
 
+## v1.5.2-patch.1
+
+- Backport : fix a regression
+  (_the PPeak+ button was not functioning anymore_)
+
 ## v1.5.2
 
 - improve pressure control

diff --git a/srcs/sysclock.cpp b/srcs/sysclock.cpp
@@ -7,58 +7,60 @@
 
 #pragma once
 
-#include "Arduino.h"
+// This file is disabled for now because it uses the PH1 pin and so breaks the PPeak+ button
 
-/**
- * @brief  System Clock Configuration
- * @note   SYSCLK = 100000000 Hz for STM32F411xE, SYSCLK = 84000000 Hz for STM32F401xE
- */
-// cppcheck-suppress unusedFunction
-extern "C" void SystemClock_Config(void) {
-    RCC_OscInitTypeDef RCC_OscInitStruct = {};
-    RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+// #include "Arduino.h"
 
-    /* Configure the main internal regulator output voltage */
-    __HAL_RCC_PWR_CLK_ENABLE();
-#if defined(STM32F401xE)
-    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-#elif defined(STM32F411xE)
-    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-#else
-#error "Wrong product line specified"
-#endif
-    /* Initializes the CPU, AHB and APB busses clocks */
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-    RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
-    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-#if defined(STM32F401xE)
-    RCC_OscInitStruct.PLL.PLLM = 8;
-    RCC_OscInitStruct.PLL.PLLN = 336;
-    RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
-    RCC_OscInitStruct.PLL.PLLQ = 7;
-#else /* STM32F411xE */
-    RCC_OscInitStruct.PLL.PLLM = 4;
-    RCC_OscInitStruct.PLL.PLLN = 100;
-    RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
-    RCC_OscInitStruct.PLL.PLLQ = 4;
-#endif
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-        Error_Handler();
-    }
-    /* Initializes the CPU, AHB and APB busses clocks */
-    RCC_ClkInitStruct.ClockType =
-        RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+// /**
+//  * @brief  System Clock Configuration
+//  * @note   SYSCLK = 100000000 Hz for STM32F411xE, SYSCLK = 84000000 Hz for STM32F401xE
+//  */
+// // cppcheck-suppress unusedFunction
+// extern "C" void SystemClock_Config(void) {
+//     RCC_OscInitTypeDef RCC_OscInitStruct = {};
+//     RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
 
-#if defined(STM32F401xE)
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
-#else /* STM32F411xE */
-    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
-#endif
-        Error_Handler();
-    }
-}
+//     /* Configure the main internal regulator output voltage */
+//     __HAL_RCC_PWR_CLK_ENABLE();
+// #if defined(STM32F401xE)
+//     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+// #elif defined(STM32F411xE)
+//     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+// #else
+// #error "Wrong product line specified"
+// #endif
+//     /* Initializes the CPU, AHB and APB busses clocks */
+//     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+//     RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+//     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+//     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+// #if defined(STM32F401xE)
+//     RCC_OscInitStruct.PLL.PLLM = 8;
+//     RCC_OscInitStruct.PLL.PLLN = 336;
+//     RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
+//     RCC_OscInitStruct.PLL.PLLQ = 7;
+// #else /* STM32F411xE */
+//     RCC_OscInitStruct.PLL.PLLM = 4;
+//     RCC_OscInitStruct.PLL.PLLN = 100;
+//     RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+//     RCC_OscInitStruct.PLL.PLLQ = 4;
+// #endif
+//     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+//         Error_Handler();
+//     }
+//     /* Initializes the CPU, AHB and APB busses clocks */
+//     RCC_ClkInitStruct.ClockType =
+//         RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+//     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+//     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+//     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+//     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+// #if defined(STM32F401xE)
+//     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+// #else /* STM32F411xE */
+//     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
+// #endif
+//         Error_Handler();
+//     }
+// }