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Your self-hosted, globally interconnected microblogging community

Ruby 47,600 7,072 Updated Jan 25, 2025

An extremely fast Python package and project manager, written in Rust.

Rust 36,959 1,014 Updated Jan 26, 2025

Sail model for the CHERI addition to RISC-V

Isabelle 3 1 Updated Jan 2, 2025

An open source Python package that generates hardware pinout diagrams as SVG images.

Python 396 20 Updated Mar 31, 2022

C++ chess library

C++ 94 26 Updated Jan 22, 2025

ConFuzz is an advanced FPGA configuration engine fuzzing and rapid prototyping framework based on boofuzz and OpenOCD.

Python 13 3 Updated Nov 29, 2024
C++ 24 4 Updated Jan 24, 2025
Go 1 2 Updated Aug 7, 2024

Style and Grammar Checker for 25+ Languages

Java 12,707 1,412 Updated Jan 25, 2025
C++ 338 34 Updated Dec 25, 2024

Package manager and build abstraction tool for FPGA/ASIC development

Python 1,234 255 Updated Jan 16, 2025

rp2040 firmware for Sonata

C 4 3 Updated Oct 31, 2024

Software, build flows and examples for the Sonata System

C++ 7 10 Updated Jan 23, 2025

👌 Support for --remote and friends.

Python 1,793 82 Updated Sep 29, 2023

Synthesisable SIMT-style RISC-V GPGPU

Assembly 30 8 Updated Jan 23, 2025

RISC-V processor framework with plugable pipelines

Haskell 7 3 Updated Dec 19, 2024

A RISC-V TestRIG Verification Engine based on QuickCheck

Haskell 7 10 Updated Jan 21, 2025

Sail code model of the CHERIoT ISA

TeX 34 10 Updated Jan 9, 2025

Demo board for TT4 and beyond

20 6 Updated Jan 8, 2025

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

Python 59 32 Updated Jan 23, 2025

ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks

C 1,141 291 Updated Jan 24, 2025

Side-channel analysis setup for OpenTitan

Jupyter Notebook 29 27 Updated Jan 16, 2025
SystemVerilog 80 5 Updated Apr 16, 2024

A free and strong UCI chess engine

C++ 12,219 2,367 Updated Jan 25, 2025

The CHERI TG aims to standardize a CHERI extension to RISC-V for both RV32 and RV64.

Dockerfile 1 2 Updated Oct 2, 2024

Design files and associated documentation for Sonata PCB, part of the Sunburst Project

ANTLR 14 2 Updated Jan 20, 2025

Open-source high performance AXI4-based HyperRAM memory controller

Verilog 61 12 Updated Oct 6, 2022

Fork of LLVM adding CHERIoT, based on the CHERI LLVM fork

C++ 6 7 Updated Jan 22, 2025

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 1,733 593 Updated Jan 25, 2025
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