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Changed the ibexc_top_tracing ports to match ibexc_top
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HU90m committed Mar 13, 2024
1 parent 64be312 commit 5551e68
Showing 1 changed file with 13 additions and 7 deletions.
20 changes: 13 additions & 7 deletions rtl/ibexc_top_tracing.sv
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,10 @@
module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808,
parameter bit DbgTriggerEn = 1'b1,
parameter int unsigned DbgHwBreakNum = 2,
parameter int unsigned MHPMCounterNum = 0,
parameter rv32b_e RV32B = RV32BNone,
parameter int unsigned HeapBase = 32'h2001_0000,
parameter int unsigned TSMapBase = 32'h2004_0000, // 4kB default
parameter int unsigned TSMapSize = 1024, // in words
Expand Down Expand Up @@ -60,7 +64,6 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
output logic tsmap_cs_o,
output logic [15:0] tsmap_addr_o,
input logic [31:0] tsmap_rdata_i,
input logic [6:0] tsmap_rdata_intg_i, // not used in ibexc_top
input logic [MMRegDinW-1:0] mmreg_corein_i,
output logic [MMRegDoutW-1:0] mmreg_coreout_o,
output logic cheri_fatal_err_o,
Expand All @@ -85,7 +88,10 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(

// CPU Control Signals
input fetch_enable_t fetch_enable_i,
output logic core_sleep_o
output logic core_sleep_o,
output logic alert_minor_o,
output logic alert_major_internal_o,
output logic alert_major_bus_o
);


Expand Down Expand Up @@ -135,15 +141,15 @@ module ibex_top_tracing import ibex_pkg::*; import cheri_pkg::*; #(
assign unused_rvfi_ext_debug_req = rvfi_ext_debug_req;
assign unused_rvfi_ext_mcycle = rvfi_ext_mcycle;

ibex_top #(
ibexc_top #(
.DmHaltAddr (DmHaltAddr ),
.DmExceptionAddr (DmExceptionAddr ),
.MHPMCounterNum (13 ),
.MHPMCounterNum (MHPMCounterNum),
.MHPMCounterWidth (40),
.DbgTriggerEn (1'b1),
.DbgHwBreakNum (4),
.DbgTriggerEn (DbgTriggerEn),
.DbgHwBreakNum (DbgHwBreakNum ),
.RV32E (1'b0),
.RV32B (RV32BFull),
.RV32B (RV32B),
.WritebackStage (1'b1),
.BranchPredictor (1'b0),
.CHERIoTEn (1'b1),
Expand Down

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