Merge branch 'master' into PEA_beta

make/jdk/src/classes/build/tools/cldrconverter/CLDRConverter.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2023, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2024, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -1289,25 +1289,58 @@ private static Map<Locale, String> coverageLevelsMap() throws Exception {
      */
     private static void generateTZDBShortNamesMap() throws IOException {
         Files.walk(Path.of(tzDataDir), 1, FileVisitOption.FOLLOW_LINKS)
-            .filter(p -> p.toFile().isFile())
+            .filter(p -> p.toFile().isFile() && !p.endsWith("jdk11_backward"))
             .forEach(p -> {
                 try {
                     String zone = null;
                     String rule = null;
                     String format = null;
+                    boolean inVanguard = false;
+                    boolean inRearguard = false;
                     for (var line : Files.readAllLines(p)) {
-                        if (line.contains("#STDOFF")) continue;
+                        // Interpret the line in rearguard mode so that STD/DST
+                        // correctly handles negative DST cases, such as "GMT/IST"
+                        // vs. "IST/GMT" case for Europe/Dublin
+                        if (inVanguard) {
+                            if (line.startsWith("# Rearguard")) {
+                                inVanguard = false;
+                                inRearguard = true;
+                            }
+                            continue;
+                        } else if (line.startsWith("# Vanguard")) {
+                            inVanguard = true;
+                            continue;
+                        }
+                        if (inRearguard) {
+                            if (line.startsWith("# End of rearguard")) {
+                                inRearguard = false;
+                                continue;
+                            } else {
+                                if (line.startsWith("#\t")) {
+                                    line = line.substring(1); // omit #
+                                }
+                            }
+                        }
+                        if (line.isBlank() || line.matches("^[ \t]*#.*")) {
+                            // ignore blank/comment lines
+                            continue;
+                        }
+                        // remove comments in-line
                         line = line.replaceAll("[ \t]*#.*", "");
 
                         // Zone line
                         if (line.startsWith("Zone")) {
+                            if (zone != null) {
+                                tzdbShortNamesMap.put(zone, format + NBSP + rule);
+                            }
                             var zl = line.split("[ \t]+", -1);
                             zone = zl[1];
                             rule = zl[3];
                             format = zl[4];
                         } else {
                             if (zone != null) {
-                                if (line.isBlank()) {
+                                if (line.startsWith("Rule") ||
+                                    line.startsWith("Link")) {
                                     tzdbShortNamesMap.put(zone, format + NBSP + rule);
                                     zone = null;
                                     rule = null;

make/modules/java.instrument/Lib.gmk

@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2011, 2022, Oracle and/or its affiliates. All rights reserved.
+# Copyright (c) 2011, 2024, Oracle and/or its affiliates. All rights reserved.
 # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 #
 # This code is free software; you can redistribute it and/or modify it
@@ -47,7 +47,7 @@ $(eval $(call SetupJdkLibrary, BUILD_LIBINSTRUMENT, \
     LDFLAGS_macosx := -L$(call FindLibDirForModule, java.base), \
     LDFLAGS_aix := -L$(SUPPORT_OUTPUTDIR)/native/java.base, \
     LIBS := $(JDKLIB_LIBS), \
-    LIBS_unix := -ljava -ljvm $(LIBZ_LIBS), \
+    LIBS_unix := $(LIBZ_LIBS), \
     LIBS_linux := -ljli $(LIBDL), \
     LIBS_aix := -liconv -ljli_static $(LIBDL), \
     LIBS_macosx := -ljli -liconv -framework Cocoa -framework Security \

src/demo/share/jfc/J2Ddemo/java2d/Intro.java

@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (c) 2007, 2018, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2007, 2024, Oracle and/or its affiliates. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -1716,7 +1716,7 @@ public Contributors(int beg, int end, Surface surf) {
                 this.beginning = beg;
                 this.ending = end;
                 fm = surf.getMetrics(font);
-                java.util.Arrays.sort(members);
+                Arrays.sort(members);
                 cast.add("CONTRIBUTORS");
                 cast.add(" ");
                 cast.addAll(Arrays.asList(members));

src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
@@ -282,7 +282,8 @@ void LIR_Assembler::osr_entry() {
         __ bind(L);
       }
 #endif
-      __ ldp(r19, r20, Address(OSR_buf, slot_offset));
+      __ ldr(r19, Address(OSR_buf, slot_offset));
+      __ ldr(r20, Address(OSR_buf, slot_offset + BytesPerWord));
       __ str(r19, frame_map()->address_for_monitor_lock(i));
       __ str(r20, frame_map()->address_for_monitor_object(i));
     }

src/hotspot/cpu/aarch64/globalDefinitions_aarch64.hpp

@@ -42,8 +42,12 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
 // and Operational Models for ARMv8"
 #define CPU_MULTI_COPY_ATOMIC
 
+// The expected size in bytes of a cache line.
 #define DEFAULT_CACHE_LINE_SIZE 64
 
+// The default padding size for data structures to avoid false sharing.
+#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE
+
 // According to the ARMv8 ARM, "Concurrent modification and execution
 // of instructions can lead to the resulting instruction performing
 // any behavior that can be achieved by executing any sequence of

src/hotspot/cpu/aarch64/templateTable_aarch64.cpp

@@ -3603,11 +3603,9 @@ void TemplateTable::_new() {
   // get InstanceKlass
   __ load_resolved_klass_at_offset(r4, r3, r4, rscratch1);
 
-  // make sure klass is initialized & doesn't have finalizer
-  // make sure klass is fully initialized
-  __ ldrb(rscratch1, Address(r4, InstanceKlass::init_state_offset()));
-  __ cmp(rscratch1, (u1)InstanceKlass::fully_initialized);
-  __ br(Assembler::NE, slow_case);
+  // make sure klass is initialized
+  assert(VM_Version::supports_fast_class_init_checks(), "Optimization requires support for fast class initialization checks");
+  __ clinit_barrier(r4, rscratch1, nullptr /*L_fast_path*/, &slow_case);
 
   // get instance_size in InstanceKlass (scaled to a count of bytes)
   __ ldrw(r3,

src/hotspot/cpu/aarch64/vm_version_aarch64.hpp

@@ -165,6 +165,7 @@ enum Ampere_CPU_Model {
   static int dcache_line_size() { return _dcache_line_size; }
   static int get_initial_sve_vector_length()  { return _initial_sve_vector_length; };
 
+  // Aarch64 supports fast class initialization checks
   static bool supports_fast_class_init_checks() { return true; }
   constexpr static bool supports_stack_watermark_barrier() { return true; }
 

src/hotspot/cpu/arm/globalDefinitions_arm.hpp

@@ -49,8 +49,12 @@ const bool HaveVFP = true;
 // arm32 is not specified as multi-copy-atomic
 // So we must not #define CPU_MULTI_COPY_ATOMIC
 
+// The expected size in bytes of a cache line.
 #define DEFAULT_CACHE_LINE_SIZE 64
 
+// The default padding size for data structures to avoid false sharing.
+#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE
+
 #define STUBROUTINES_MD_HPP    "stubRoutines_arm.hpp"
 #define INTERP_MASM_MD_HPP     "interp_masm_arm.hpp"
 #define TEMPLATETABLE_MD_HPP   "templateTable_arm.hpp"

src/hotspot/cpu/ppc/globalDefinitions_ppc.hpp

@@ -48,9 +48,12 @@ const bool CCallingConventionRequiresIntsAsLongs = true;
 // PPC64 is not specified as multi-copy-atomic
 // So we must not #define CPU_MULTI_COPY_ATOMIC
 
-// The expected size in bytes of a cache line, used to pad data structures.
+// The expected size in bytes of a cache line.
 #define DEFAULT_CACHE_LINE_SIZE 128
 
+// The default padding size for data structures to avoid false sharing.
+#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE
+
 #define SUPPORT_RESERVED_STACK_AREA
 
 // If UseSIGTRAP is active, we only use the poll bit and no polling page.

src/hotspot/cpu/ppc/vm_version_ppc.hpp

@@ -91,7 +91,7 @@ class VM_Version: public Abstract_VM_Version {
   // Override Abstract_VM_Version implementation
   static void print_platform_virtualization_info(outputStream*);
 
-  // PPC64 supports fast class initialization checks for static methods.
+  // PPC64 supports fast class initialization checks
   static bool supports_fast_class_init_checks() { return true; }
   constexpr static bool supports_stack_watermark_barrier() { return true; }
 

src/hotspot/cpu/riscv/globalDefinitions_riscv.hpp

@@ -50,6 +50,10 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
 
 #define USE_POINTERS_TO_REGISTER_IMPL_ARRAY
 
+// The expected size in bytes of a cache line.
 #define DEFAULT_CACHE_LINE_SIZE 64
 
+// The default padding size for data structures to avoid false sharing.
+#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE
+
 #endif // CPU_RISCV_GLOBALDEFINITIONS_RISCV_HPP

src/hotspot/cpu/riscv/vm_version_riscv.hpp

@@ -209,6 +209,9 @@ class VM_Version : public Abstract_VM_Version {
   constexpr static bool supports_stack_watermark_barrier() { return true; }
 
   static bool supports_on_spin_wait() { return UseZihintpause; }
+
+  // RISCV64 supports fast class initialization checks
+  static bool supports_fast_class_init_checks() { return true; }
 };
 
 #endif // CPU_RISCV_VM_VERSION_RISCV_HPP

src/hotspot/cpu/s390/globalDefinitions_s390.hpp

@@ -48,6 +48,9 @@ const bool CCallingConventionRequiresIntsAsLongs = true;
 // The expected size in bytes of a cache line, used to pad data structures.
 #define DEFAULT_CACHE_LINE_SIZE 256
 
+// The default padding size for data structures to avoid false sharing.
+#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE
+
 #define SUPPORT_RESERVED_STACK_AREA
 
 #endif // CPU_S390_GLOBALDEFINITIONS_S390_HPP

src/hotspot/cpu/s390/vm_version_s390.hpp

@@ -410,7 +410,7 @@ class VM_Version: public Abstract_VM_Version {
   // Override Abstract_VM_Version implementation
   static void print_platform_virtualization_info(outputStream*);
 
-  // s390 supports fast class initialization checks for static methods.
+  // s390 supports fast class initialization checks
   static bool supports_fast_class_init_checks() { return true; }
 
   // CPU feature query functions

src/hotspot/cpu/x86/globalDefinitions_x86.hpp

@@ -38,29 +38,18 @@ const bool CCallingConventionRequiresIntsAsLongs = false;
 
 #define CPU_MULTI_COPY_ATOMIC
 
-// The expected size in bytes of a cache line, used to pad data structures.
-#if COMPILER1_AND_COMPILER2
-  #ifdef _LP64
-    // tiered, 64-bit, large machine
-    #define DEFAULT_CACHE_LINE_SIZE 128
-    #define OM_CACHE_LINE_SIZE 64
-  #else
-    // tiered, 32-bit, medium machine
-    #define DEFAULT_CACHE_LINE_SIZE 64
-  #endif
-#elif defined(COMPILER1)
-  // pure C1, 32-bit, small machine
-  // i486 was the last Intel chip with 16-byte cache line size
-  #define DEFAULT_CACHE_LINE_SIZE 32
-#elif defined(COMPILER2)
-  #ifdef _LP64
-    // pure C2, 64-bit, large machine
-    #define DEFAULT_CACHE_LINE_SIZE 128
-    #define OM_CACHE_LINE_SIZE 64
-  #else
-    // pure C2, 32-bit, medium machine
-    #define DEFAULT_CACHE_LINE_SIZE 64
-  #endif
+// The expected size in bytes of a cache line.
+#define DEFAULT_CACHE_LINE_SIZE 64
+
+// The default padding size for data structures to avoid false sharing.
+#ifdef _LP64
+// The common wisdom is that adjacent cache line prefetchers on some hardware
+// may pull two cache lines on access, so we have to pessimistically assume twice
+// the cache line size for padding. TODO: Check if this is still true for modern
+// hardware. If not, DEFAULT_CACHE_LINE_SIZE might as well suffice.
+#define DEFAULT_PADDING_SIZE (DEFAULT_CACHE_LINE_SIZE*2)
+#else
+#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE
 #endif
 
 #if defined(COMPILER2)

src/hotspot/cpu/x86/macroAssembler_x86.cpp

@@ -1871,92 +1871,6 @@ void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
 }
 #endif
 
-void MacroAssembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
-  if ((UseAVX > 0) && (dst != src)) {
-    xorpd(dst, dst);
-  }
-  Assembler::cvtss2sd(dst, src);
-}
-
-void MacroAssembler::cvtss2sd(XMMRegister dst, Address src) {
-  if (UseAVX > 0) {
-    xorpd(dst, dst);
-  }
-  Assembler::cvtss2sd(dst, src);
-}
-
-void MacroAssembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
-  if ((UseAVX > 0) && (dst != src)) {
-    xorps(dst, dst);
-  }
-  Assembler::cvtsd2ss(dst, src);
-}
-
-void MacroAssembler::cvtsd2ss(XMMRegister dst, Address src) {
-  if (UseAVX > 0) {
-    xorps(dst, dst);
-  }
-  Assembler::cvtsd2ss(dst, src);
-}
-
-void MacroAssembler::cvtsi2sdl(XMMRegister dst, Register src) {
-  if (UseAVX > 0) {
-    xorpd(dst, dst);
-  }
-  Assembler::cvtsi2sdl(dst, src);
-}
-
-void MacroAssembler::cvtsi2sdl(XMMRegister dst, Address src) {
-  if (UseAVX > 0) {
-    xorpd(dst, dst);
-  }
-  Assembler::cvtsi2sdl(dst, src);
-}
-
-void MacroAssembler::cvtsi2ssl(XMMRegister dst, Register src) {
-  if (UseAVX > 0) {
-    xorps(dst, dst);
-  }
-  Assembler::cvtsi2ssl(dst, src);
-}
-
-void MacroAssembler::cvtsi2ssl(XMMRegister dst, Address src) {
-  if (UseAVX > 0) {
-    xorps(dst, dst);
-  }
-  Assembler::cvtsi2ssl(dst, src);
-}
-
-#ifdef _LP64
-void MacroAssembler::cvtsi2sdq(XMMRegister dst, Register src) {
-  if (UseAVX > 0) {
-    xorpd(dst, dst);
-  }
-  Assembler::cvtsi2sdq(dst, src);
-}
-
-void MacroAssembler::cvtsi2sdq(XMMRegister dst, Address src) {
-  if (UseAVX > 0) {
-    xorpd(dst, dst);
-  }
-  Assembler::cvtsi2sdq(dst, src);
-}
-
-void MacroAssembler::cvtsi2ssq(XMMRegister dst, Register src) {
-  if (UseAVX > 0) {
-    xorps(dst, dst);
-  }
-  Assembler::cvtsi2ssq(dst, src);
-}
-
-void MacroAssembler::cvtsi2ssq(XMMRegister dst, Address src) {
-  if (UseAVX > 0) {
-    xorps(dst, dst);
-  }
-  Assembler::cvtsi2ssq(dst, src);
-}
-#endif  // _LP64
-
 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
   assert(rscratch != noreg || always_reachable(adr), "missing");
 

src/hotspot/cpu/x86/macroAssembler_x86.hpp

@@ -800,23 +800,6 @@ class MacroAssembler: public Assembler {
 
   void cmpxchgptr(Register reg, Address adr);
 
-
-  // cvt instructions
-  void cvtss2sd(XMMRegister dst, XMMRegister src);
-  void cvtss2sd(XMMRegister dst, Address src);
-  void cvtsd2ss(XMMRegister dst, XMMRegister src);
-  void cvtsd2ss(XMMRegister dst, Address src);
-  void cvtsi2sdl(XMMRegister dst, Register src);
-  void cvtsi2sdl(XMMRegister dst, Address src);
-  void cvtsi2ssl(XMMRegister dst, Register src);
-  void cvtsi2ssl(XMMRegister dst, Address src);
-#ifdef _LP64
-  void cvtsi2sdq(XMMRegister dst, Register src);
-  void cvtsi2sdq(XMMRegister dst, Address src);
-  void cvtsi2ssq(XMMRegister dst, Register src);
-  void cvtsi2ssq(XMMRegister dst, Address src);
-#endif
-
   void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
 
   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }