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Re-enabled PLIC for Ariane
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Signed-off-by: Matt Rossouw <[email protected]>
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omeh-a authored and Indanz committed Nov 6, 2024
1 parent 9edd270 commit 65825d4
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Showing 2 changed files with 5 additions and 9 deletions.
5 changes: 3 additions & 2 deletions include/drivers/irq/riscv_plic0.h
Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,9 @@
!defined(CONFIG_PLAT_POLARFIRE) && \
!defined(CONFIG_PLAT_QEMU_RISCV_VIRT) && \
!defined(CONFIG_PLAT_ROCKETCHIP_ZCU102) && \
!defined(CONFIG_PLAT_STAR64)
#error "Check if this platform suppots a PLIC."
!defined(CONFIG_PLAT_STAR64) && \
!defined(CONFIG_PLAT_ARIANE)
#error "Check if this platform supports a PLIC."
#endif

/* tell the kernel we have the set trigger feature */
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9 changes: 2 additions & 7 deletions src/plat/ariane/config.cmake
Original file line number Diff line number Diff line change
Expand Up @@ -16,15 +16,10 @@ if(KernelPlatformAriane)
config_set(KernelOpenSBIPlatform OPENSBI_PLATFORM "fpga/ariane")
list(APPEND KernelDTSList "tools/dts/ariane.dts")
list(APPEND KernelDTSList "src/plat/ariane/overlay-ariane.dts")
# This is an experimental platform that supports accessing peripherals, but
# the status of support for external interrupts via a PLIC is unclear and
# may differ depending on the version that is synthesized. Declaring no
# interrupts and using the dummy PLIC driver seems the best option for now
# to avoid confusion or even crashes.
declare_default_headers(
MAX_IRQ 30
TIMER_FREQUENCY 25000000
MAX_IRQ 0
INTERRUPT_CONTROLLER drivers/irq/riscv_plic_dummy.h
INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
)
else()
unset(KernelPlatformFirstHartID CACHE)
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