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Fix Verilator simulations #351

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Fix Verilator simulations #351

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4 changes: 2 additions & 2 deletions tb/core/tb_top_verilator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ void dump_memory()
{
errno = 0;
std::ofstream mem_file;
svLogicVecVal addr = {0};
svLogicVecVal addr = {0, 0};

mem_file.exceptions(std::ofstream::failbit | std::ofstream::badbit);
try {
Expand All @@ -84,7 +84,7 @@ void dump_memory()

std::cout << "finished dumping memory" << std::endl;

} catch (std::ofstream::failure e) {
} catch (std::ofstream::failure &e) {
std::cerr << "exception opening/reading/closing file memory_dump.bin\n";
}
}
3 changes: 3 additions & 0 deletions tb/verilator-model/Makefile
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Expand Up @@ -55,12 +55,15 @@ VSRC = dp_ram.sv \
../../rtl/riscv_decoder.sv \
../../rtl/riscv_int_controller.sv \
../../rtl/riscv_ex_stage.sv \
../../rtl/riscv_ff_one.sv \
../../rtl/riscv_fetch_fifo.sv \
../../rtl/riscv_hwloop_controller.sv \
../../rtl/riscv_hwloop_regs.sv \
../../rtl/riscv_id_stage.sv \
../../rtl/riscv_if_stage.sv \
../../rtl/riscv_load_store_unit.sv \
../../rtl/riscv_mult.sv \
../../rtl/riscv_popcnt.sv \
../../rtl/riscv_prefetch_buffer.sv \
../../rtl/riscv_prefetch_L0_buffer.sv \
../../rtl/riscv_register_file.sv \
Expand Down
13 changes: 5 additions & 8 deletions tb/verilator-model/top.sv
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Expand Up @@ -65,20 +65,19 @@ module top
#(
.PULP_CLUSTER(PULP_CLUSTER),
.FPU(FPU),
.PULP_ZFINX(PULP_ZFINX),
.DM_HALTADDRESS(DM_HALTADDRESS)
.PULP_ZFINX(PULP_ZFINX)
)
riscv_core_i
(
.clk_i ( clk_i ),
.rst_ni ( rstn_i ),

.clock_en_i ( 1'b1 ),
.test_en_i ( 1'b0 ),
.scan_cg_en_i ( 1'b0 ),

.boot_addr_i ( BOOT_ADDR ),
.core_id_i ( 4'h0 ),
.cluster_id_i ( 6'h0 ),
.dm_halt_addr_i ( DM_HALTADDRESS ),
.hart_id_i ( 32'h0 ),

.instr_addr_o ( instr_addr ),
.instr_req_o ( instr_req ),
Expand Down Expand Up @@ -118,9 +117,7 @@ module top
.debug_req_i ( debug_req_i ),

.fetch_enable_i ( fetch_enable_i ),
.core_busy_o ( core_busy_o ),

.fregfile_disable_i ( 1'b0 ));
.core_busy_o ( core_busy_o ));

// Instantiate the memory

Expand Down