Fusesoc and Linter

.github/workflows/lint.yml

@@ -0,0 +1,18 @@
+on: [push, pull_request]
+
+jobs:
+  lint:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v1
+      - name: Lint Verilog sources with Verilator
+        uses: librecores/ci-fusesoc-action@master
+        with:
+          command: 'run'
+          core: 'openhw:cv32e40p:core'
+          target: 'lint'
+          tool: 'verilator'
+          pre-run-command: |
+            pip3 install git+https://github.com/olofk/fusesoc@master
+            make

.gitignore

@@ -15,6 +15,6 @@ TAGS
 .build-rtl
 .lib-rtl
 .opt-rtl
-/build
+build/
 /Bender.lock
 /Bender.local

cv32e40p.core

@@ -0,0 +1,79 @@
+CAPI=2:
+# Copyright OpenHW Group contributors.
+# Licensed under the Solderpad Hardware Licence, Version 2.0 , see LICENSE for details.
+name: "openhw:cv32e40p:core:0.1"
+description: "CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform"
+
+filesets:
+  files_rtl:
+# First need this upstream
+#    depend:
+#      - pulp-platform.org::fpnew
+    files:
+# Temporarily added until fpnew is upstream
+      - rtl/fpnew/src/common_cells/include/common_cells/registers.svh: { is_include_file: true, include_path: "rtl/fpnew/src/common_cells/include" }
+      - rtl/fpnew/src/fpnew_pkg.sv
+      - rtl/fpnew/src/fpnew_cast_multi.sv
+      - rtl/fpnew/src/fpnew_classifier.sv
+      - rtl/fpnew/src/fpnew_divsqrt_multi.sv
+      - rtl/fpnew/src/fpnew_fma.sv
+      - rtl/fpnew/src/fpnew_fma_multi.sv
+      - rtl/fpnew/src/fpnew_noncomp.sv
+      - rtl/fpnew/src/fpnew_opgroup_block.sv
+      - rtl/fpnew/src/fpnew_opgroup_fmt_slice.sv
+      - rtl/fpnew/src/fpnew_opgroup_multifmt_slice.sv
+      - rtl/fpnew/src/fpnew_rounding.sv
+      - rtl/fpnew/src/fpnew_top.sv
+# /Temporarily added until fpnew is upstream
+      - rtl/include/cv32e40p_apu_macros.sv: {is_include_file: true}
+      - rtl/include/cv32e40p_config.sv: {is_include_file: true}
+      - rtl/include/cv32e40p_apu_core_package.sv
+      - rtl/include/cv32e40p_defines.sv
+      - rtl/include/cv32e40p_tracer_defines.sv
+      - rtl/cv32e40p_if_stage.sv
+      - rtl/cv32e40p_tracer.sv
+      - rtl/cv32e40p_sim_clock_gate.sv
+      - rtl/cv32e40p_cs_registers.sv
+      - rtl/cv32e40p_register_file_ff.sv
+      - rtl/cv32e40p_load_store_unit.sv
+      - rtl/cv32e40p_id_stage.sv
+      - rtl/cv32e40p_decoder.sv
+      - rtl/cv32e40p_compressed_decoder.sv
+      - rtl/cv32e40p_fetch_fifo.sv
+      - rtl/cv32e40p_prefetch_buffer.sv
+      - rtl/cv32e40p_prefetch_controller.sv
+      - rtl/cv32e40p_hwloop_regs.sv
+      - rtl/cv32e40p_hwloop_controller.sv
+      - rtl/cv32e40p_mult.sv
+      - rtl/cv32e40p_register_file_test_wrap.sv
+      - rtl/cv32e40p_int_controller.sv
+      - rtl/cv32e40p_ex_stage.sv
+      - rtl/cv32e40p_alu_div.sv
+      - rtl/cv32e40p_alu.sv
+      - rtl/cv32e40p_ff_one.sv
+      - rtl/cv32e40p_obi_interface.sv
+      - rtl/cv32e40p_popcnt.sv
+      - rtl/cv32e40p_pmp.sv
+      - rtl/cv32e40p_apu_disp.sv
+      - rtl/cv32e40p_controller.sv
+      - rtl/cv32e40p_core.sv
+    file_type: systemVerilogSource
+  files_lint_verilator:
+    files:
+      - verilator_waiver.vlt
+    file_type: systemVerilogSource
+
+targets:
+  default: &default
+    filesets:
+      - tool_verilator ? (files_lint_verilator)
+      - files_rtl
+  lint:
+    <<: *default
+    default_tool: verilator
+    toplevel: cv32e40p_core
+    tools:
+      verilator:
+        mode: lint-only
+        verilator_options:
+          - "-Wall"

python-requirements.txt

@@ -0,0 +1 @@
+fusesoc>=1.11

tb/core/Makefile.fusesoc

@@ -0,0 +1,7 @@
+build:
+	fusesoc --cores-root=../../ run --target=sim --setup --build openhw:cv32e40p:testbench
+
+run:
+	build/openhw_cv32e40p_testbench_0.1/sim-verilator/Vtb_top_verilator "+firmware=firmware/firmware.hex"
+
+.PHONY: build run

tb/core/tb_top_verilator.cpp

@@ -69,7 +69,7 @@ void dump_memory()
 {
     errno = 0;
     std::ofstream mem_file;
-    svLogicVecVal addr = {0};
+    svLogicVecVal addr = {0, 0};
 
     mem_file.exceptions(std::ofstream::failbit | std::ofstream::badbit);
     try {
@@ -84,7 +84,7 @@ void dump_memory()
 
         std::cout << "finished dumping memory" << std::endl;
 
-    } catch (std::ofstream::failure e) {
+    } catch (std::ofstream::failure &e) {
         std::cerr << "exception opening/reading/closing file memory_dump.bin\n";
     }
 }

tb/core/testbench.core

@@ -0,0 +1,30 @@
+CAPI=2:
+# Copyright OpenHW Group contributors.
+# Licensed under the Solderpad Hardware Licence, Version 2.0 , see LICENSE for details.
+name: "openhw:cv32e40p:testbench:0.1"
+description: "Testbench for CV32E40P"
+filesets:
+  files_sim_verilator:
+    depend:
+      - openhw:cv32e40p:core
+    files:
+      - tb_top_verilator.sv
+      - riscv_wrapper.sv
+      - mm_ram.sv
+      - dp_ram.sv
+      - amo_shim.sv
+      - tb_top_verilator.cpp: { file_type: cppSource }
+      - verilator_waiver.vlt
+    file_type: systemVerilogSource
+
+targets:
+  sim:
+    filesets:
+      - files_sim_verilator
+    toplevel: tb_top_verilator
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: cc
+        verilator_options:
+          - "--trace"

tb/verilator-model/Makefile

@@ -1,114 +1,6 @@
-# Copyright 2017 Embecosm Limited <www.embecosm.com>
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#    http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
+build:
+	fusesoc --cores-root=../../ run --target=sim --setup --build openhw:cv32e40p:verilator-model
+run:
+	build/openhw_cv32e40p_verilator-model_0.1/sim-verilator/Vtop "+firmware=firmware/firmware.hex"
 
-# Makefile for Verilator model of RI5CY
-# Contributor: Jeremy Bennett <[email protected]>
-
-# Tools
-
-VERILATOR = verilator
-VDIR = obj_dir
-CPPFLAGS = -I$(VDIR) `pkg-config --cflags verilator`
-CXXFLAGS = -Wall -Werror -std=c++11 -Wno-aligned-new
-CXX = g++
-LD = g++
-
-# Testbench
-
-SRC = testbench.cpp
-
-OBJS = testbench.o
-
-EXE = testbench
-
-# top module name
-
-TOP = top
-
-# Verilator elements
-
-VSRC = dp_ram.sv                                 \
-       ram.sv                                    \
-       top.sv                                    \
-       ../../rtl/fpnew/src/fpnew_pkg.sv          \
-       ../../rtl/include/cv32e40p_apu_core_package.sv     \
-       ../../rtl/include/cv32e40p_defines.sv        \
-       ../../rtl/include/cv32e40p_tracer_defines.sv \
-       ../../rtl/cv32e40p_register_file_test_wrap.sv      \
-       ../../rtl/cv32e40p_sim_clock_gate.sv      \
-       ../../rtl/cv32e40p_alu.sv                    \
-       ../../rtl/cv32e40p_alu_div.sv                \
-       ../../rtl/cv32e40p_compressed_decoder.sv     \
-       ../../rtl/cv32e40p_controller.sv             \
-       ../../rtl/cv32e40p_cs_registers.sv           \
-       ../../rtl/cv32e40p_decoder.sv                \
-       ../../rtl/cv32e40p_int_controller.sv         \
-       ../../rtl/cv32e40p_ex_stage.sv               \
-       ../../rtl/cv32e40p_hwloop_controller.sv      \
-       ../../rtl/cv32e40p_hwloop_regs.sv            \
-       ../../rtl/cv32e40p_id_stage.sv               \
-       ../../rtl/cv32e40p_if_stage.sv               \
-       ../../rtl/cv32e40p_load_store_unit.sv        \
-       ../../rtl/cv32e40p_mult.sv                   \
-       ../../rtl/cv32e40p_prefetch_buffer.sv        \
-       ../../rtl/cv32e40p_register_file_ff.sv       \
-       ../../rtl/cv32e40p_core.sv                   \
-       ../../rtl/cv32e40p_apu_disp.sv               \
-       ../../rtl/cv32e40p_pmp.sv
-
-VINC = ../../rtl/include
-
-VOBJS = $(VDIR)/verilated.o       \
-        $(VDIR)/verilated_vcd_c.o
-
-VLIB = $(VDIR)/V$(TOP)__ALL.a
-
-VSMK = V$(TOP).mk
-VMK  = $(VDIR)/$(VSMK)
-
-# Build the executable
-all: $(EXE)
-
-$(EXE): $(VLIB) $(VOBJS) $(OBJS)
-	$(LD) -o $@ $(OBJS) $(VLIB) $(VOBJS)
-
-$(VOBJS): $(VMK)
-	for f in $@; \
-	do \
-		sf=$$(basename $$f); \
-		$(MAKE) -C $(VDIR) -f $(VSMK) $$sf; \
-	done
-
-$(VLIB): $(VMK)
-	make -C $(VDIR) -f V$(TOP).mk
-
-$(VDIR)/$(TOP): $(VDIR) $(VMK)
-	$(MAKE) -C $(VDIR) -f $(VSMK)
-
-$(VDIR):
-	mkdir -p $@
-
-$(VMK): $(VSRC)
-	verilator -O3 -CFLAGS "-O3 -g3 -std=gnu++11" \
-                  -Wno-CASEINCOMPLETE -Wno-LITENDIAN -Wno-UNOPT \
-	          -Wno-UNOPTFLAT -Wno-WIDTH -Wno-fatal -Wno-BLKANDNBLK \
-		  --top-module top \
-	          --Mdir $(VDIR) --trace -DPULP_FPGA_EMUL -cc \
-	          +incdir+$(VINC) $(VSRC) $(SRC) --exe
-
-
-.PHONY: clean
-clean:
-	$(RM) -r $(VDIR)
-	$(RM) $(EXE) $(OBJS)
+.PHONY: build

tb/verilator-model/testbench.core

@@ -0,0 +1,28 @@
+CAPI=2:
+# Copyright OpenHW Group contributors.
+# Licensed under the Solderpad Hardware Licence, Version 2.0 , see LICENSE for details.
+name: "openhw:cv32e40p:verilator-model:0.1"
+description: "Verilator testbench for CV32E40P"
+filesets:
+  files_sim_verilator:
+    depend:
+      - openhw:cv32e40p:core
+    files:
+      - dp_ram.sv
+      - ram.sv
+      - top.sv
+      - testbench.cpp: { file_type: cppSource }
+    file_type: systemVerilogSource
+
+targets:
+  sim:
+    filesets:
+      - files_sim_verilator
+    toplevel: top
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: cc
+        verilator_options:
+          - "-Wno-fatal"
+          - "--trace"

tb/verilator-model/top.sv

@@ -65,20 +65,19 @@ module top
      #(
         .PULP_CLUSTER(PULP_CLUSTER),
         .FPU(FPU),
-        .PULP_ZFINX(PULP_ZFINX),
-        .DM_HALTADDRESS(DM_HALTADDRESS)
+        .PULP_ZFINX(PULP_ZFINX)
        )
    core_i
      (
       .clk_i                  ( clk_i                 ),
       .rst_ni                 ( rstn_i                ),
 
       .clock_en_i             ( 1'b1                  ),
-      .test_en_i              ( 1'b0                  ),
+      .scan_cg_en_i           ( 1'b0                  ),
 
       .boot_addr_i            ( BOOT_ADDR             ),
-      .core_id_i              ( 4'h0                  ),
-      .cluster_id_i           ( 6'h0                  ),
+      .dm_halt_addr_i         ( DM_HALTADDRESS        ),
+      .hart_id_i              ( 32'h0                 ),
 
       .instr_addr_o           ( instr_addr            ),
       .instr_req_o            ( instr_req             ),
@@ -110,17 +109,13 @@ module top
       .irq_timer_i            ( 1'b0                  ),
       .irq_external_i         ( 1'b0                  ),
       .irq_fast_i             ( 15'b0                 ),
-      .irq_nmi_i              ( 1'b0                  ),
-      .irq_fastx_i            ( 32'b0                 ),
       .irq_ack_o              ( irq_ack_o             ),
       .irq_id_o               ( irq_id_o              ),
 
       .debug_req_i            ( debug_req_i           ),
 
       .fetch_enable_i         ( fetch_enable_i        ),
-      .core_busy_o            ( core_busy_o           ),
-
-      .fregfile_disable_i     ( 1'b0                  ));
+      .core_busy_o            ( core_busy_o           ));
 
    // Instantiate the memory