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    8 repositories

    • Logisim

      Public
      Mastering Digital Logic Design with Logisim: From Basics to CPU
      Apache License 2.0
      •0•6•0•0•Updated Oct 31, 2024Oct 31, 2024

    • RISCV_Single_Cycle_Core

      Public
      This repository contains the design files of RISC-V Single Cycle Core
      Verilog
      •
      Apache License 2.0
      •8•32•0•0•Updated Dec 14, 2023Dec 14, 2023

    • PY_UVM_Framework

      Public
      This repo contain the PY-UVM Framework for different RISC-V Cores
      Python
      •
      Apache License 2.0
      •0•31•0•0•Updated Sep 16, 2023Sep 16, 2023

    • SAP_FPU_Verification

      Public
      This repository contains the Graphical User Interface (GUI) of the Verification Environment of SAP-FPU.
      Apache License 2.0
      •1•1•0•0•Updated Sep 14, 2023Sep 14, 2023

    • PY_UVM_Tutorial

      Public
      This repository will contain all the files regarding the Py-UVM tutorial
      Python
      •
      Apache License 2.0
      •0•2•0•0•Updated Aug 21, 2023Aug 21, 2023

    • RISCV_Pipeline_Core

      Public
      This repository contains the design files of RISC-V Pipeline Core
      Verilog
      •
      Apache License 2.0
      •8•35•0•0•Updated May 11, 2023May 11, 2023

    • .github

      Public
      We are from Microelectronics Research Lab (MERL-DSU). MERL is an non-profitable organization with an ambitious plan to lead Microelectronics Research & Development in Pakistan. MERL is working with a Vision to enable Pakistan to become a recognized global player in the microelectronics industry.
      0•0•0•0•Updated Apr 28, 2023Apr 28, 2023

    • SAP_FPU

      Public
      This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
      Verilog
      •
      Apache License 2.0
      •4•18•0•0•Updated Mar 17, 2023Mar 17, 2023