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hal/imxrt117x: fix Fractional PLL configuration and enable PLL1 #372
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Unit Test Results7 958 tests 7 416 ✅ 40m 23s ⏱️ Results for commit 1727871. ♻️ This comment has been updated with latest results. |
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No, I don't want new compilation warnings! Please think how it can be avoided (and keeping the implementation).
Not sure if we would like to unanimously enable 1GHz PLL on every project, maybe it should be configurable by board_config.h
?
IMHO we could define functions with |
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Fractional PLLs (SYS_PLL1, PLL_AUDIO and PLL_VIDEO) are configured through VDDSOC2 registers, which are accessed via the Analog IP interface. JIRA: RTOS-963
PLL1 and its dividers can be enabled in board_config.h JIRA: RTOS-963
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Description
Fractional PLLs are configured throught registers in VDDSOC2, which are accessible through Analog IP interface.
ENET module in iMX RT1170 EVK/EVKB needs PLL1 to work.
Motivation and Context
This change is needed to properly initialize, set bypass and deinitialize Fractional PLLs (SYS_PLL1, PLL_AUDIO, PLL_VIDEO).
For this to work and the tests to pass, phoenix-rtos/phoenix-rtos-project#1248 is needed
related: phoenix-rtos/phoenix-rtos-project#1251
Types of changes
How Has This Been Tested?
armv7m7-imxrt117x-evk
.Checklist:
Special treatment