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hal/imxrt117x: fix Fractional PLL configuration and enable PLL1 #372

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@julianuziemblo julianuziemblo commented Dec 9, 2024

Description

Fractional PLLs are configured throught registers in VDDSOC2, which are accessible through Analog IP interface.
ENET module in iMX RT1170 EVK/EVKB needs PLL1 to work.

Motivation and Context

This change is needed to properly initialize, set bypass and deinitialize Fractional PLLs (SYS_PLL1, PLL_AUDIO, PLL_VIDEO).

For this to work and the tests to pass, phoenix-rtos/phoenix-rtos-project#1248 is needed

related: phoenix-rtos/phoenix-rtos-project#1251

Types of changes

  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)
  • Chore (refactoring, style fixes, git/CI config, submodule management, no code logic changes)

How Has This Been Tested?

  • Already covered by automatic testing.
  • New test added: (add PR link here).
  • Tested by hand on: armv7m7-imxrt117x-evk.

Checklist:

  • My change requires a change to the documentation.
  • I have updated the documentation accordingly.
  • I have added tests to cover my changes.
  • All new and existing linter checks and tests passed.
  • My changes generate no new compilation warnings for any of the targets:

Special treatment

agkaminski
agkaminski previously approved these changes Dec 10, 2024
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github-actions bot commented Dec 10, 2024

Unit Test Results

7 958 tests   7 416 ✅  40m 23s ⏱️
  470 suites    542 💤
    1 files        0 ❌

Results for commit 1727871.

♻️ This comment has been updated with latest results.

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No, I don't want new compilation warnings! Please think how it can be avoided (and keeping the implementation).

Not sure if we would like to unanimously enable 1GHz PLL on every project, maybe it should be configurable by board_config.h?

@nalajcie
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No, I don't want new compilation warnings! Please think how it can be avoided (and keeping the implementation).

IMHO we could define functions with __attribute__((unused)) - the most readable solution for me :)

Fractional PLLs (SYS_PLL1, PLL_AUDIO and PLL_VIDEO) are
configured through VDDSOC2 registers, which are accessed
via the Analog IP interface.

JIRA: RTOS-963
PLL1 and its dividers can be enabled in board_config.h

JIRA: RTOS-963
@julianuziemblo julianuziemblo force-pushed the julianuziemblo/enet-imxrt117x-evkb branch from 0b4f165 to 1727871 Compare February 3, 2025 14:10
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3 participants