Lower default FPGA frequency for Genesys2 board

Changes to FPU made timing constraints to thight. Changed to more conservative
values so we do not need to constantly adjust the default constraints when the
critical path grows a little bit longer.

README.md

@@ -221,18 +221,18 @@ PULPissimo is running at. If you didn't change anything in the synthesis script,
 
 
 | Clock Domain   | Default Frequency on Genesys2 board |
-|----------------|------------------------------------ |
-| Core Frequency | 40MHz                               |
-| SoC Frequency  | 20MHz                               |
+|----------------|-------------------------------------|
+| Core Frequency | 20 MHz                              |
+| SoC Frequency  | 10 MHz                              |
 
 
 We need to override two weakly defined variables in our source code to configure the SDK to use these frequencies:
 ```C
 #include <stdio.h>
 #include <rt/rt_api.h>
 
-int __rt_fpga_fc_frequency = 40000000;
-int __rt_fpga_periph_frequency = 20000000;
+int __rt_fpga_fc_frequency = 20000000;
+int __rt_fpga_periph_frequency = 10000000;
 
 int main()
 {

fpga/pulpissimo-genesys2/fpga-settings.mk

@@ -1,9 +1,9 @@
 export BOARD=genesys2
 export XILINX_PART=xc7k325tffg900-2
 export XILINX_BOARD=digilentinc.com:genesys2:part0:1.1
-export FC_CLK_PERIOD_NS=25
-export PER_CLK_PERIOD_NS=50
-export SLOW_CLK_PERIOD_NS=50
+export FC_CLK_PERIOD_NS=50
+export PER_CLK_PERIOD_NS=100
+export SLOW_CLK_PERIOD_NS=100
 #Must also change the localparam 'L2_BANK_SIZE' in pulp_soc.sv accordingly
 export INTERLEAVED_BANK_SIZE=28672
 #Must also change the localparam 'L2_BANK_SIZE_PRI' in pulp_soc.sv accordingly