unify 32-bit encodings for load/store/amo to use RV64 versions (#385)

fixes #372

due to the conflict with Zilsd meaning we lost access to LC/SC in RV32,
it seems wise to move all to the RV64 encodings which have no current
conflicts.

all is subject to change on ARC review.

src/csv/CHERI_ISA.csv

@@ -1,6 +1,6 @@
 "Mnemonic","RV32","RV64","Base ISA (I/E)","Zish4add","Zabhlrsc","{cheri_default_ext_name}","{cheri_base_ext_name}","Valid Modes","A","Zicbo[mpz]","Zba","C or Zca","Zcb","Zcf","Zcd","Zcmp","Zcmt","Zfh","F","D","V","H","XLEN dependent encoding","funct3","major opcode","Format","{cheri_int_mode_name} mnemonic RV32","{cheri_int_mode_name} mnemonic RV64","Function","illegal insn if (1)","OR illegal insn if (2)","OR illegal insn if (3)","illegal insn if (4)","illegal insn if (5)","illegal insn if (6)","illegal insn if (7)","illegal insn if (8)"
-"LC","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","✔","3","LOAD (RV32) / MISC_MEM (RV64)","I-type","","","Load cap via int pointer","","","","","","","",""
-"SC","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","✔","","STORE","S-type","","","Store cap via int pointer","","","","","","","",""
+"LC","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","3","MISC_MEM","I-type","","","Load cap via int pointer","","","","","","","",""
+"SC","✔","✔","","","","✔","✔","Both","","","","","","","","","","","","","","","","","STORE","S-type","","","Store cap via int pointer","","","","","","","",""
 "C.LCSP","✔","✔","","","","","✔","{cheri_cap_mode_name}","","","","✔","","","","","","","","","","","✔","","C2","","C.FLWSP","C.FLDSP","Load cap capability, SP relative ","","","","","","","",""
 "C.SCSP","✔","✔","","","","","✔","{cheri_cap_mode_name}","","","","✔","","","","","","","","","","","✔","","C2","","C.FSWSP","C.FSDSP","Store cap capability, SP relative ","","","","","","","",""
 "C.LC","✔","✔","","","","","✔","{cheri_cap_mode_name}","","","","✔","","","","","","","","","","","✔","","C0","","C.FLW","C.FLD","Load cap capability","","","","","","","",""
@@ -79,17 +79,17 @@
 "PREFETCH.R","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","","","OP-IMM","","","","Prefetch instruction cache line, always valid","","","","","","","",""
 "PREFETCH.W","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","","","OP-IMM","","","","Prefetch read-only data cache line","","","","","","","",""
 "PREFETCH.I","✔","✔","✔","","","✔","✔","Both","","✔","","","","","","","","","","","","","","","OP-IMM","","","","Prefetch writeable data cache line","","","","","","","",""
-"LR.C","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","✔","","AMO","","","","Load reserved capability","","","","","","","",""
+"LR.C","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Load reserved capability","","","","","","","",""
 "LR.D","","","✔","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Load reserved double","","","","","","","",""
 "LR.W","","","✔","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Load reserved word","","","","","","","",""
 "LR.H","✔","✔","","","✔","✔","✔","Both","","","","","","","","","","","","","","","","","AMO","","","","Load reserved half","","","","","","","",""
 "LR.B","✔","✔","","","✔","✔","✔","Both","","","","","","","","","","","","","","","","","AMO","","","","Load reserved byte","","","","","","","",""
-"SC.C","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","✔","","AMO","","","","Store conditional capability","","","","","","","",""
+"SC.C","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Store conditional capability","","","","","","","",""
 "SC.D","","","✔","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Store conditional double","","","","","","","",""
 "SC.W","","","✔","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Store conditional word","","","","","","","",""
 "SC.H","✔","✔","","","✔","✔","✔","Both","","","","","","","","","","","","","","","","","AMO","","","","Store conditional half","","","","","","","",""
 "SC.B","✔","✔","","","✔","✔","✔","Both","","","","","","","","","","","","","","","","","AMO","","","","Store conditional byte","","","","","","","",""
-"AMOSWAP.C","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","✔","","AMO","","","","Atomic swap of cap ","","","","","","","",""
+"AMOSWAP.C","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Atomic swap of cap ","","","","","","","",""
 "AMO<OP>.W","✔","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Atomic op of word","","","","","","","",""
 "AMO<OP>.D","","✔","","","","✔","✔","Both","✔","","","","","","","","","","","","","","","","AMO","","","","Atomic op of double","","","","","","","",""
 "C.FLW","✔","","","","","✔","","{cheri_int_mode_name}","","","","","","","","","","","✔","","","","","","C0","","","","Load floating point word capability","Xstatus.fs==0","","","","","","",""

src/insns/amoswap_32bit_cap.adoc

@@ -3,13 +3,9 @@
 [#AMOSWAP_C,reftext="AMOSWAP.C"]
 ==== AMOSWAP.C
 
-NOTE: The RV64 encoding is intended to also allocate the encoding for AMOSWAP.Q for RV128.
-
 Synopsis::
 Atomic Operation (AMOSWAP.C), 32-bit encoding
 
-include::xlen_variable_warning.adoc[]
-
 {cheri_cap_mode_name} Mnemonic::
 `amoswap.c cd, cs2, offset(cs1)`
 

src/insns/load_16bit_cap_sprel.adoc

@@ -11,6 +11,8 @@ see <<C_LCSP>>.
 Synopsis::
 Capability loads (C.LC, C.LCSP), 16-bit encodings
 
+include::xlen_variable_warning.adoc[]
+
 {cheri_cap_mode_name} Mnemonics::
 `c.lc cd', offset(cs1')` +
 `c.lc cd', offset(csp)`

src/insns/load_16bit_fp_sp.adoc

@@ -27,12 +27,6 @@ Standard floating point load instructions, authorised by the capability in <<ddc
 NOTE: These instructions are available in RV32 {cheri_int_mode_name} only.
 In {cheri_cap_mode_name} they are remapped to <<C.LC>>/<<C.LCSP>>.
 
-NOTE: In {cheri_int_mode_name}, these instructions may be remapped to
-other encodings by future RV32 only extensions such as Zilsd.
-If this is the case, then the Zilsd encodings will be valid in
-{cheri_int_mode_name} only. In
-{cheri_cap_mode_name} the instructions will still be <<C.LC>>/<<C.LCSP>>.
-
 include::load_exceptions.adoc[]
 
 Prerequisites for {cheri_int_mode_name}::

src/insns/load_32bit_cap.adoc

@@ -16,8 +16,6 @@ Load capability
 {cheri_int_mode_name} Mnemonic::
 `lc cd, offset(rs1)`
 
-include::xlen_variable_warning.adoc[]
-
 Encoding::
 include::wavedrom/loadcap.adoc[]
 

src/insns/load_res_cap_32bit.adoc

@@ -3,13 +3,9 @@
 [#LR_C,reftext="LR.C"]
 ==== LR.C
 
-NOTE: The RV64 encoding is intended to also allocate the encoding for LR.Q for RV128.
-
 Synopsis::
 Load Reserved Capability (LR.C), 32-bit encodings
 
-include::xlen_variable_warning.adoc[]
-
 {cheri_cap_mode_name} Mnemonic::
 `lr.c cd, 0(cs1)`
 

src/insns/store_16bit_cap_sprel.adoc

@@ -9,7 +9,7 @@ see <<C_SCSP>>.
 ==== C.SCSP
 
 Synopsis::
-Stores (C.SC, C.SCSP), 16-bit encodings
+Capability stores (C.SC, C.SCSP), 16-bit encodings
 
 include::xlen_variable_warning.adoc[]
 

src/insns/store_16bit_fp_sp.adoc

@@ -30,12 +30,6 @@ Standard floating point store instructions, authorised by the capability in <<dd
 NOTE: These instructions are available in RV32 {cheri_int_mode_name} only.
 In {cheri_cap_mode_name} they are remapped to <<C.SC>>/<<C.SCSP>>.
 
-NOTE: In {cheri_int_mode_name}, these instructions may be remapped to
-other encodings by future RV32 only extensions such as Zilsd.
-If this is the case, then the Zilsd encodings will be valid in
-{cheri_int_mode_name} only. In
-{cheri_cap_mode_name} the instructions will still be <<C.SC>>/<<C.SCSP>>.
-
 include::store_exceptions.adoc[]
 
 Prerequisites::

src/insns/store_32bit_cap.adoc

@@ -14,8 +14,6 @@ Store capability
 {cheri_int_mode_name} Mnemonic::
 `sc cs2, offset(rs1)`
 
-include::xlen_variable_warning.adoc[]
-
 Encoding::
 include::wavedrom/storecap.adoc[]
 

src/insns/store_cond_cap_32bit.adoc

@@ -3,13 +3,9 @@
 [#SC_C,reftext="SC.C"]
 ==== SC.C
 
-NOTE: The RV64 encoding is intended to also allocate the encoding for SC.Q for RV128.
-
 Synopsis::
 Store Conditional (SC.C), 32-bit encoding
 
-include::xlen_variable_warning.adoc[]
-
 {cheri_cap_mode_name} Mnemonic::
 `sc.c rd, cs2, 0(cs1)`
 

src/insns/wavedrom/amoswap_cap.adoc

@@ -5,7 +5,7 @@
 {reg: [
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'cd',       attr: ['5', 'rdest[4:0]'], type: 3},
-  {bits: 3,  name: 'funct3',   attr: ['3', 'width', 'rv32: .C=011', 'rv64: .C=100'], type: 8},
+  {bits: 3,  name: 'funct3',   attr: ['3', 'width', '.C=100'], type: 8},
   {bits: 5,  name: 'cs1',      attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'cs2',      attr: ['5', 'src'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},

src/insns/wavedrom/load_res_cap.adoc

@@ -5,7 +5,7 @@
 {reg: [
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'cd',       attr: ['5', 'rdest[4:0]'], type: 3},
-  {bits: 3,  name: 'funct3',   attr: ['3', 'rv32: .C=011', 'rv64: .C=100'], type: 8},
+  {bits: 3,  name: 'funct3',   attr: ['3', '.C=100'], type: 8},
   {bits: 5,  name: 'cs1/rs1',  attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'funct5',   attr: ['5', 'LR.*=00000'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},

src/insns/wavedrom/loadcap.adoc

@@ -4,9 +4,9 @@
 ....
 {reg: [
   {bits: 7,  name: 'opcode',    attr: ['7', 'MISCMEM=0001111','LOAD=0000011',], type: 8},
-  {bits: 5,  name: 'cd', attr: ['5', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'rv64: LC=100', 'rv32: LC=011'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'cd',        attr: ['5', 'dest'], type: 2},
+  {bits: 3,  name: 'funct3',    attr: ['3', 'LC=100'], type: 8},
+  {bits: 5,  name: 'rs1/cs1',   attr: ['5', 'base'], type: 4},
   {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3},
 ]}
 ....

src/insns/wavedrom/store_cond_cap.adoc

@@ -5,7 +5,7 @@
 {reg: [
   {bits: 7,  name: 'opcode',   attr: ['7', 'AMO=0101111'], type: 8},
   {bits: 5,  name: 'rd',       attr: ['5', 'rdest[4:0]'], type: 3},
-  {bits: 3,  name: 'funct3',   attr: ['3', 'width', 'rv32: .C=011','rv64: .C=100'], type: 8},
+  {bits: 3,  name: 'funct3',   attr: ['3', 'width', '.C=100'], type: 8},
   {bits: 5,  name: 'cs1/rs1',  attr: ['5', 'base'], type: 4},
   {bits: 5,  name: 'cs2',      attr: ['5', 'src'],  type: 4},
   {bits: 1,  name: 'rl',       attr: ['1', 'rl'],  type: 4},

src/insns/wavedrom/storecap.adoc

@@ -3,11 +3,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',   attr: ['7', 'STORE=0100011'], type: 8},
-  {bits: 5,  name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3},
-  {bits: 3,  name: 'funct3', attr: ['3', 'rv64: SC=100', 'rv32: SC=011'], type: 8},
-  {bits: 5,  name: 'rs1/cs1', attr: ['5', 'base'], type: 4},
-  {bits: 5,  name: 'cs2', attr: ['5', 'src'], type: 4},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'STORE=0100011'], type: 8},
+  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'offset[4:0]'], type: 3},
+  {bits: 3,  name: 'funct3',    attr: ['3', 'SC=100'], type: 8},
+  {bits: 5,  name: 'rs1/cs1',   attr: ['5', 'base'], type: 4},
+  {bits: 5,  name: 'cs2',       attr: ['5', 'src'], type: 4},
   {bits: 7,  name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3},
 ]}
 ....